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159 lines
4.6 KiB
Rust
159 lines
4.6 KiB
Rust
5 years ago
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// SPDX-License-Identifier: MIT
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//
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// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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//! GPIO driver.
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use crate::{arch, arch::sync::NullLock, interface};
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use core::ops;
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use register::{mmio::ReadWrite, register_bitfields};
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// GPIO registers.
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//
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// Descriptions taken from
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// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
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register_bitfields! {
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u32,
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/// GPIO Function Select 1
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GPFSEL1 [
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/// Pin 15
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FSEL15 OFFSET(15) NUMBITS(3) [
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Input = 0b000,
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Output = 0b001,
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AltFunc0 = 0b100 // PL011 UART RX
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],
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/// Pin 14
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FSEL14 OFFSET(12) NUMBITS(3) [
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Input = 0b000,
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Output = 0b001,
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AltFunc0 = 0b100 // PL011 UART TX
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]
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],
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/// GPIO Pull-up/down Clock Register 0
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GPPUDCLK0 [
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/// Pin 15
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PUDCLK15 OFFSET(15) NUMBITS(1) [
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NoEffect = 0,
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AssertClock = 1
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],
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/// Pin 14
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PUDCLK14 OFFSET(14) NUMBITS(1) [
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NoEffect = 0,
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AssertClock = 1
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]
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]
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}
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#[allow(non_snake_case)]
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#[repr(C)]
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pub struct RegisterBlock {
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pub GPFSEL0: ReadWrite<u32>, // 0x00
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pub GPFSEL1: ReadWrite<u32, GPFSEL1::Register>, // 0x04
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pub GPFSEL2: ReadWrite<u32>, // 0x08
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pub GPFSEL3: ReadWrite<u32>, // 0x0C
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pub GPFSEL4: ReadWrite<u32>, // 0x10
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pub GPFSEL5: ReadWrite<u32>, // 0x14
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__reserved_0: u32, // 0x18
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GPSET0: ReadWrite<u32>, // 0x1C
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GPSET1: ReadWrite<u32>, // 0x20
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__reserved_1: u32, //
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GPCLR0: ReadWrite<u32>, // 0x28
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__reserved_2: [u32; 2], //
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GPLEV0: ReadWrite<u32>, // 0x34
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GPLEV1: ReadWrite<u32>, // 0x38
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__reserved_3: u32, //
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GPEDS0: ReadWrite<u32>, // 0x40
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GPEDS1: ReadWrite<u32>, // 0x44
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__reserved_4: [u32; 7], //
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GPHEN0: ReadWrite<u32>, // 0x64
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GPHEN1: ReadWrite<u32>, // 0x68
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__reserved_5: [u32; 10], //
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pub GPPUD: ReadWrite<u32>, // 0x94
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pub GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>, // 0x98
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pub GPPUDCLK1: ReadWrite<u32>, // 0x9C
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}
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/// The driver's private data.
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struct GPIOInner {
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base_addr: usize,
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}
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/// Deref to RegisterBlock.
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impl ops::Deref for GPIOInner {
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type Target = RegisterBlock;
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fn deref(&self) -> &Self::Target {
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unsafe { &*self.ptr() }
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}
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}
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impl GPIOInner {
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const fn new(base_addr: usize) -> GPIOInner {
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GPIOInner { base_addr }
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}
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/// Return a pointer to the register block.
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fn ptr(&self) -> *const RegisterBlock {
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self.base_addr as *const _
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}
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/// Map PL011 UART as standard output.
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///
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/// TX to pin 14
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/// RX to pin 15
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pub fn map_pl011_uart(&mut self) {
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// Map to pins.
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self.GPFSEL1
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.modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0);
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// Enable pins 14 and 15.
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self.GPPUD.set(0);
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arch::spin_for_cycles(150);
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self.GPPUDCLK0
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.write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
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arch::spin_for_cycles(150);
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self.GPPUDCLK0.set(0);
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}
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}
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//--------------------------------------------------------------------------------------------------
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// BSP-public
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//--------------------------------------------------------------------------------------------------
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use interface::sync::Mutex;
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/// The driver's main struct.
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pub struct GPIO {
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inner: NullLock<GPIOInner>,
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}
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impl GPIO {
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pub const unsafe fn new(base_addr: usize) -> GPIO {
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GPIO {
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inner: NullLock::new(GPIOInner::new(base_addr)),
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}
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}
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// Only visible to other BSP code.
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5 years ago
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pub fn map_pl011_uart(&self) {
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5 years ago
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let mut r = &self.inner;
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5 years ago
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r.lock(|inner| inner.map_pl011_uart());
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5 years ago
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}
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}
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//--------------------------------------------------------------------------------------------------
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// OS interface implementations
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//--------------------------------------------------------------------------------------------------
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impl interface::driver::DeviceDriver for GPIO {
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fn compatible(&self) -> &str {
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"GPIO"
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}
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}
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