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@ -99,8 +99,8 @@ diff -uNr 05_safe_globals/Cargo.toml 06_drivers_gpio_uart/Cargo.toml
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r0 = "0.2.*"
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# Optional dependencies
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cortex-a = { version = "2.*", optional = true }
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+register = { version = "0.3.*", optional = true }
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cortex-a = { version = "2.8.x", optional = true }
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+register = { version = "0.4.x", optional = true }
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diff -uNr 05_safe_globals/src/arch/aarch64.rs 06_drivers_gpio_uart/src/arch/aarch64.rs
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--- 05_safe_globals/src/arch/aarch64.rs
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@ -125,7 +125,7 @@ diff -uNr 05_safe_globals/src/arch/aarch64.rs 06_drivers_gpio_uart/src/arch/aarc
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diff -uNr 05_safe_globals/src/bsp/driver/bcm/bcm2xxx_gpio.rs 06_drivers_gpio_uart/src/bsp/driver/bcm/bcm2xxx_gpio.rs
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--- 05_safe_globals/src/bsp/driver/bcm/bcm2xxx_gpio.rs
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+++ 06_drivers_gpio_uart/src/bsp/driver/bcm/bcm2xxx_gpio.rs
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@@ -0,0 +1,157 @@
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@@ -0,0 +1,145 @@
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+// SPDX-License-Identifier: MIT
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+//
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+// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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@ -134,7 +134,7 @@ diff -uNr 05_safe_globals/src/bsp/driver/bcm/bcm2xxx_gpio.rs 06_drivers_gpio_uar
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+
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+use crate::{arch, arch::sync::NullLock, interface};
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+use core::ops;
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+use register::{mmio::ReadWrite, register_bitfields};
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+use register::{mmio::ReadWrite, register_bitfields, register_structs};
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+
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+// GPIO registers.
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+//
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@ -177,33 +177,21 @@ diff -uNr 05_safe_globals/src/bsp/driver/bcm/bcm2xxx_gpio.rs 06_drivers_gpio_uar
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+ ]
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+}
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+
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+#[allow(non_snake_case)]
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+#[repr(C)]
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+pub struct RegisterBlock {
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+ pub GPFSEL0: ReadWrite<u32>, // 0x00
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+ pub GPFSEL1: ReadWrite<u32, GPFSEL1::Register>, // 0x04
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+ pub GPFSEL2: ReadWrite<u32>, // 0x08
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+ pub GPFSEL3: ReadWrite<u32>, // 0x0C
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+ pub GPFSEL4: ReadWrite<u32>, // 0x10
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+ pub GPFSEL5: ReadWrite<u32>, // 0x14
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+ __reserved_0: u32, // 0x18
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+ GPSET0: ReadWrite<u32>, // 0x1C
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+ GPSET1: ReadWrite<u32>, // 0x20
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+ __reserved_1: u32, //
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+ GPCLR0: ReadWrite<u32>, // 0x28
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+ __reserved_2: [u32; 2], //
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+ GPLEV0: ReadWrite<u32>, // 0x34
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+ GPLEV1: ReadWrite<u32>, // 0x38
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+ __reserved_3: u32, //
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+ GPEDS0: ReadWrite<u32>, // 0x40
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+ GPEDS1: ReadWrite<u32>, // 0x44
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+ __reserved_4: [u32; 7], //
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+ GPHEN0: ReadWrite<u32>, // 0x64
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+ GPHEN1: ReadWrite<u32>, // 0x68
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+ __reserved_5: [u32; 10], //
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+ pub GPPUD: ReadWrite<u32>, // 0x94
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+ pub GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>, // 0x98
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+ pub GPPUDCLK1: ReadWrite<u32>, // 0x9C
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+register_structs! {
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+ #[allow(non_snake_case)]
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+ RegisterBlock {
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+ (0x00 => GPFSEL0: ReadWrite<u32>),
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+ (0x04 => GPFSEL1: ReadWrite<u32, GPFSEL1::Register>),
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+ (0x08 => GPFSEL2: ReadWrite<u32>),
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+ (0x0C => GPFSEL3: ReadWrite<u32>),
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+ (0x10 => GPFSEL4: ReadWrite<u32>),
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+ (0x14 => GPFSEL5: ReadWrite<u32>),
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+ (0x18 => _reserved1),
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+ (0x94 => GPPUD: ReadWrite<u32>),
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+ (0x98 => GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>),
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+ (0x9C => GPPUDCLK1: ReadWrite<u32>),
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+ (0xA0 => @END),
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+ }
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+}
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+
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+/// The driver's private data.
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@ -287,7 +275,7 @@ diff -uNr 05_safe_globals/src/bsp/driver/bcm/bcm2xxx_gpio.rs 06_drivers_gpio_uar
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diff -uNr 05_safe_globals/src/bsp/driver/bcm/bcm2xxx_pl011_uart.rs 06_drivers_gpio_uart/src/bsp/driver/bcm/bcm2xxx_pl011_uart.rs
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--- 05_safe_globals/src/bsp/driver/bcm/bcm2xxx_pl011_uart.rs
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+++ 06_drivers_gpio_uart/src/bsp/driver/bcm/bcm2xxx_pl011_uart.rs
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@@ -0,0 +1,313 @@
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@@ -0,0 +1,315 @@
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+// SPDX-License-Identifier: MIT
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+//
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+// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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@ -296,7 +284,7 @@ diff -uNr 05_safe_globals/src/bsp/driver/bcm/bcm2xxx_pl011_uart.rs 06_drivers_gp
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+
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+use crate::{arch, arch::sync::NullLock, interface};
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+use core::{fmt, ops};
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+use register::{mmio::*, register_bitfields};
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+use register::{mmio::*, register_bitfields, register_structs};
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+
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+// PL011 UART registers.
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+//
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@ -399,19 +387,21 @@ diff -uNr 05_safe_globals/src/bsp/driver/bcm/bcm2xxx_pl011_uart.rs 06_drivers_gp
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+ ]
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+}
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+
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+#[allow(non_snake_case)]
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+#[repr(C)]
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+pub struct RegisterBlock {
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+ DR: ReadWrite<u32>, // 0x00
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+ __reserved_0: [u32; 5], // 0x04
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+ FR: ReadOnly<u32, FR::Register>, // 0x18
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+ __reserved_1: [u32; 2], // 0x1c
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+ IBRD: WriteOnly<u32, IBRD::Register>, // 0x24
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+ FBRD: WriteOnly<u32, FBRD::Register>, // 0x28
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+ LCRH: WriteOnly<u32, LCRH::Register>, // 0x2C
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+ CR: WriteOnly<u32, CR::Register>, // 0x30
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+ __reserved_2: [u32; 4], // 0x34
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+ ICR: WriteOnly<u32, ICR::Register>, // 0x44
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+register_structs! {
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+ #[allow(non_snake_case)]
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+ RegisterBlock {
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+ (0x00 => DR: ReadWrite<u32>),
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+ (0x04 => _reserved1),
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+ (0x18 => FR: ReadOnly<u32, FR::Register>),
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+ (0x1c => _reserved2),
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+ (0x24 => IBRD: WriteOnly<u32, IBRD::Register>),
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+ (0x28 => FBRD: WriteOnly<u32, FBRD::Register>),
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+ (0x2c => LCRH: WriteOnly<u32, LCRH::Register>),
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+ (0x30 => CR: WriteOnly<u32, CR::Register>),
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+ (0x34 => _reserved3),
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+ (0x44 => ICR: WriteOnly<u32, ICR::Register>),
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+ (0x48 => @END),
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+ }
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+}
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+
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+/// The driver's mutex protected part.
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Andre Richter
5 years ago