Remove memory barrier again

Upon further reading, found out that RPi3 features an A53 CPU, which
is one of the ARMv8-A variants that in fact does _not_ have
out-of-order execution.

05_uart0/src/main.rs

@@ -54,10 +54,6 @@ fn main() {
     mbox.buffer[6] = 0;
     mbox.buffer[7] = mbox::tag::LAST;
 
-    // Insert a memory barrier that ensures mailbox buffer setup
-    // finishes before VIDEOCORE is notified.
-    mbox::Mbox::synchronize();
-
     // send the message to the GPU and receive answer
     let serial_avail = match mbox.call(mbox::channel::PROP) {
         Err(_) => false,

05_uart0/src/mbox.rs

@@ -93,19 +93,6 @@ impl Mbox {
         }
     }
 
-    /// ARM Data Memory Barrier (DMB). Intended for use after setting
-    /// up the mailbox buffer and before calling Mbox::call().
-    ///
-    /// Prevents that CPU instruction reordering results in notifying
-    /// the VIDEOCORE about a new message before setting up the
-    /// mailbox buffer is finished.
-    #[inline(always)]
-    pub fn synchronize() {
-        unsafe {
-            asm!("DMB SY" :::: "volatile");
-        }
-    }
-
     /// Make a mailbox call. Returns Err(MboxError) on failure, Ok(()) success
     pub fn call(&mut self, channel: u32) -> Result<()> {
         // wait until we can write to the mailbox

05_uart0/src/uart.rs

@@ -77,10 +77,6 @@ impl Uart {
         mbox.buffer[7] = 0; // skip turbo setting
         mbox.buffer[8] = mbox::tag::LAST;
 
-        // Insert a memory barrier that ensures mailbox buffer setup
-        // finishes before VIDEOCORE is notified.
-        mbox::Mbox::synchronize();
-
         if let Err(_) = mbox.call(mbox::channel::PROP) {
             return Err(UartError::MailboxError); // Abort if UART clocks couldn't be set
         };