First part of tutorial: 0B_exception_levels
- Added code - Missing: READMEpull/9/head
Andre Richter
6 years ago
parent
08235093c1
commit
4b1bac7509
@ -0,0 +1,6 @@
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[target.aarch64-unknown-none]
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rustflags = [
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"-C", "link-arg=-Tlink.ld",
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"-C", "target-feature=-fp-armv8",
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"-C", "target-cpu=cortex-a53",
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]
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@ -0,0 +1,55 @@
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[[package]]
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name = "cortex-a"
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version = "2.1.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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"register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "kernel8"
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version = "0.1.0"
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dependencies = [
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"cortex-a 2.1.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"raspi3_boot 0.1.0",
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"register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "panic-abort"
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version = "0.2.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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name = "r0"
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version = "0.2.2"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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name = "raspi3_boot"
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version = "0.1.0"
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dependencies = [
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"cortex-a 2.1.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"panic-abort 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "register"
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version = "0.2.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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"tock-registers 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "tock-registers"
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version = "0.2.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[metadata]
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"checksum cortex-a 2.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "09269c0b1f2cb25c9b22f1258f4cb658164cec8f539adc53c039c54ef25d1132"
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"checksum panic-abort 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)" = "6bc796c620f27056d4ffe7c558533fd67ae5af0fd8e919fbe38de803368af73e"
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"checksum r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)" = "e2a38df5b15c8d5c7e8654189744d8e396bddc18ad48041a500ce52d6948941f"
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"checksum register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)" = "157a11ac0b1882ff4a527a92f911dd288df17367faaaa0c36f188cd61ec36fc1"
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"checksum tock-registers 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)" = "3a385d94f3f62e60445a0adb9ff8d9621faa272234530d4c0f848ec98f88e316"
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@ -0,0 +1,12 @@
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[package]
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name = "kernel8"
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version = "0.1.0"
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authors = ["Andre Richter <andre.o.richter@gmail.com>"]
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[dependencies]
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raspi3_boot = { path = "raspi3_boot" }
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cortex-a = "2.1.0"
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register = "0.2.0"
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[package.metadata.cargo-xbuild]
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sysroot_path = "../xbuild_sysroot"
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@ -0,0 +1,66 @@
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#
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# MIT License
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#
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# Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
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# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in all
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# copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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# SOFTWARE.
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#
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TARGET = aarch64-unknown-none
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OBJCOPY = cargo objcopy --
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OBJCOPY_PARAMS = --strip-all -O binary
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UTILS_CONTAINER = andrerichter/raspi3-utils
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DOCKER_CMD = docker run -it --rm -v $(shell pwd):/work -w /work
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DOCKER_TTY = --privileged -v /dev:/dev
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QEMU_CMD = qemu-system-aarch64 -M raspi3 -kernel kernel8.img
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RASPBOOT_CMD = raspbootcom /dev/ttyUSB0 kernel8.img
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all: clean kernel8.img
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target/$(TARGET)/debug/kernel8: src/main.rs
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cargo xbuild --target=$(TARGET)
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cp $@ .
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target/$(TARGET)/release/kernel8: src/main.rs
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cargo xbuild --target=$(TARGET) --release
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cp $@ .
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ifeq ($(DEBUG),1)
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kernel8: target/$(TARGET)/debug/kernel8
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else
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kernel8: target/$(TARGET)/release/kernel8
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endif
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kernel8.img: kernel8
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$(OBJCOPY) $(OBJCOPY_PARAMS) $< kernel8.img
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qemu: all
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$(DOCKER_CMD) $(UTILS_CONTAINER) $(QEMU_CMD) -serial stdio
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raspboot: all
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$(DOCKER_CMD) $(DOCKER_TTY) $(UTILS_CONTAINER) $(RASPBOOT_CMD)
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clippy:
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cargo xclippy --target=$(TARGET)
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clean:
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cargo clean
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rm -f kernel8
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@ -0,0 +1,27 @@
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# Tutorial 0B - Exception Levels
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**This is a stub**
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This tutorial covers a very exciting and central feature of the Raspberry Pi's
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Cortex-A53 processor: `Exception levels`.
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TODO: Write rest of tutorial.
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```text
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raspi3_boot::setup_and_enter_el1_from_el2::h0641a5a5302db706:
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80954: e8 03 1f aa mov x8, xzr
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80958: e9 07 00 32 orr w9, wzr, #0x3
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8095c: 4a 00 80 52 mov w10, #0x2
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80960: 0a 00 b0 72 movk w10, #0x8000, lsl #16
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80964: 09 e1 1c d5 msr CNTHCTL_EL2, x9
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80968: 68 e0 1c d5 msr CNTVOFF_EL2, x8
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8096c: 08 00 00 90 adrp x8, #0x0
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80970: 8b 78 80 52 mov w11, #0x3c4
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80974: 0a 11 1c d5 msr HCR_EL2, x10
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80978: ec 03 0d 32 orr w12, wzr, #0x80000
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8097c: 08 81 24 91 add x8, x8, #0x920
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80980: 0b 40 1c d5 msr SPSR_EL2, x11
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80984: 28 40 1c d5 msr ELR_EL2, x8
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80988: 0c 41 18 d5 msr SP_EL0, x12
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8098c: e0 03 9f d6 eret
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```
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Binary file not shown.
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@ -0,0 +1,56 @@
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/*
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* MIT License
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*
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* Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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||||
* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
|
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
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*
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* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
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* SOFTWARE.
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*/
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ENTRY(_boot_cores);
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SECTIONS
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{
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. = 0x80000;
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.text :
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{
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KEEP(*(.text.boot)) *(.text .text.*)
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}
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.rodata :
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{
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*(.rodata .rodata.*)
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}
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.data :
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{
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*(.data .data.*)
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}
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.bss ALIGN(8):
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{
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__bss_start = .;
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*(.bss .bss.*)
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*(COMMON)
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__bss_end = .;
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}
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/DISCARD/ : { *(.comment) *(.gnu*) *(.note*) *(.eh_frame*) }
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}
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@ -0,0 +1,9 @@
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[package]
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name = "raspi3_boot"
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version = "0.1.0"
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authors = ["Andre Richter <andre.o.richter@gmail.com>"]
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[dependencies]
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cortex-a = "2.1.0"
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panic-abort = "0.2.0"
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r0 = "0.2.2"
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@ -0,0 +1,131 @@
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/*
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* MIT License
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*
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* Copyright (c) 2018 Jorge Aparicio
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* Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
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*
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||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
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* SOFTWARE.
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*/
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#![deny(missing_docs)]
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#![deny(warnings)]
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#![no_std]
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//! Low-level boot of the Raspberry's processor
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extern crate cortex_a;
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extern crate panic_abort;
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extern crate r0;
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#[macro_export]
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macro_rules! entry {
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($path:path) => {
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#[export_name = "main"]
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pub unsafe fn __main() -> ! {
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// type check the given path
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let f: fn() -> ! = $path;
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f()
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}
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};
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}
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/// Reset function.
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///
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/// Initializes the bss section before calling into the user's `main()`.
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unsafe fn reset() -> ! {
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extern "C" {
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// Boundaries of the .bss section, provided by the linker script
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static mut __bss_start: u64;
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static mut __bss_end: u64;
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}
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// Zeroes the .bss section
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r0::zero_bss(&mut __bss_start, &mut __bss_end);
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extern "Rust" {
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fn main() -> !;
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}
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main()
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}
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/// Prepare and execute transition from EL2 to EL1.
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#[inline]
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fn setup_and_enter_el1_from_el2() -> ! {
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use cortex_a::{asm, regs::*};
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// Enable timer counter registers for EL1
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CNTHCTL_EL2.write(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET);
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// No offset for reading the counters
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CNTVOFF_EL2.set(0);
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// Set EL1 execution state to AArch64
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// TODO: Explain the SWIO bit
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HCR_EL2.write(HCR_EL2::RW::EL1IsAarch64 + HCR_EL2::SWIO::SET);
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// Set up a simulated exception return.
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//
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// First, fake a saved program status, where all interrupts were
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// masked and SP_EL0 was used as a stack pointer.
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SPSR_EL2.write(
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SPSR_EL2::D::Masked
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+ SPSR_EL2::A::Masked
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+ SPSR_EL2::I::Masked
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+ SPSR_EL2::F::Masked
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+ SPSR_EL2::M::EL1t,
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);
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// Second, let the link register point to reset().
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ELR_EL2.set(reset as *const () as u64);
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// Set up SP_EL0 (stack pointer), which will be used by EL1 once
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// we "return" to it.
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SP_EL0.set(0x80_000);
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// Use `eret` to "return" to EL1. This will result in execution of
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// `reset()` in EL1.
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asm::eret()
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}
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/// Entrypoint of the processor.
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///
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/// Parks all cores except core0 and checks if we started in EL2. If
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/// so, proceeds with setting up EL1.
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#[link_section = ".text.boot"]
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#[no_mangle]
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pub unsafe extern "C" fn _boot_cores() -> ! {
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use cortex_a::{asm, regs::*};
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const CORE_0: u64 = 0;
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const CORE_MASK: u64 = 0x3;
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const EL2: u32 = CurrentEL::EL::EL2.value;
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if let CORE_0 = MPIDR_EL1.get() & CORE_MASK {
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if let EL2 = CurrentEL.get() {
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setup_and_enter_el1_from_el2()
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}
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}
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// if not core0 or EL != 2, infinitely wait for events
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loop {
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asm::wfe();
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}
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}
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@ -0,0 +1,55 @@
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/*
|
||||
* MIT License
|
||||
*
|
||||
* Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
|
||||
use cortex_a::regs::*;
|
||||
|
||||
/*
|
||||
*
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* Using the CPU's counter registers
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||||
*
|
||||
*/
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/// Wait N microsec (ARM CPU only)
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pub fn wait_msec(n: u32) {
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// Get the counter frequency
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let frq = CNTFRQ_EL0.get();
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// Calculate number of ticks
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let tval = (frq as u32 / 1000) * n;
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// Set the compare value register
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CNTP_TVAL_EL0.set(tval);
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// Kick off the counting // Disable timer interrupt
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CNTP_CTL_EL0.modify(CNTP_CTL_EL0::ENABLE::SET + CNTP_CTL_EL0::IMASK::SET);
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loop {
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// ISTATUS will be one when cval ticks have passed. Continuously check it.
|
||||
if CNTP_CTL_EL0.is_set(CNTP_CTL_EL0::ISTATUS) {
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break;
|
||||
}
|
||||
}
|
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|
||||
// Disable counting again
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CNTP_CTL_EL0.modify(CNTP_CTL_EL0::ENABLE::CLEAR);
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||||
}
|
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@ -0,0 +1,75 @@
|
||||
/*
|
||||
* MIT License
|
||||
*
|
||||
* Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
|
||||
use super::MMIO_BASE;
|
||||
use register::mmio::ReadWrite;
|
||||
|
||||
// Descriptions taken from
|
||||
// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
|
||||
register_bitfields! {
|
||||
u32,
|
||||
|
||||
/// GPIO Function Select 1
|
||||
GPFSEL1 [
|
||||
/// Pin 15
|
||||
FSEL15 OFFSET(15) NUMBITS(3) [
|
||||
Input = 0b000,
|
||||
Output = 0b001,
|
||||
RXD0 = 0b100, // UART0 - Alternate function 0
|
||||
RXD1 = 0b010 // Mini UART - Alternate function 5
|
||||
|
||||
],
|
||||
|
||||
/// Pin 14
|
||||
FSEL14 OFFSET(12) NUMBITS(3) [
|
||||
Input = 0b000,
|
||||
Output = 0b001,
|
||||
TXD0 = 0b100, // UART0 - Alternate function 0
|
||||
TXD1 = 0b010 // Mini UART - Alternate function 5
|
||||
]
|
||||
],
|
||||
|
||||
/// GPIO Pull-up/down Clock Register 0
|
||||
GPPUDCLK0 [
|
||||
/// Pin 15
|
||||
PUDCLK15 OFFSET(15) NUMBITS(1) [
|
||||
NoEffect = 0,
|
||||
AssertClock = 1
|
||||
],
|
||||
|
||||
/// Pin 14
|
||||
PUDCLK14 OFFSET(14) NUMBITS(1) [
|
||||
NoEffect = 0,
|
||||
AssertClock = 1
|
||||
]
|
||||
]
|
||||
}
|
||||
|
||||
pub const GPFSEL1: *const ReadWrite<u32, GPFSEL1::Register> =
|
||||
(MMIO_BASE + 0x0020_0004) as *const ReadWrite<u32, GPFSEL1::Register>;
|
||||
|
||||
pub const GPPUD: *const ReadWrite<u32> = (MMIO_BASE + 0x0020_0094) as *const ReadWrite<u32>;
|
||||
|
||||
pub const GPPUDCLK0: *const ReadWrite<u32, GPPUDCLK0::Register> =
|
||||
(MMIO_BASE + 0x0020_0098) as *const ReadWrite<u32, GPPUDCLK0::Register>;
|
||||
@ -0,0 +1,107 @@
|
||||
/*
|
||||
* MIT License
|
||||
*
|
||||
* Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
|
||||
extern crate cortex_a;
|
||||
|
||||
#[macro_use]
|
||||
extern crate raspi3_boot;
|
||||
|
||||
#[macro_use]
|
||||
extern crate register;
|
||||
|
||||
const MMIO_BASE: u32 = 0x3F00_0000;
|
||||
|
||||
mod delays;
|
||||
mod gpio;
|
||||
mod mbox;
|
||||
mod uart;
|
||||
|
||||
use cortex_a::regs::*;
|
||||
|
||||
fn check_timer(uart: &uart::Uart) {
|
||||
uart.puts(
|
||||
"Testing EL1 access to timer registers.\n\
|
||||
Delaying for 3 seconds now.\n",
|
||||
);
|
||||
delays::wait_msec(1000);
|
||||
uart.puts("1..");
|
||||
delays::wait_msec(1000);
|
||||
uart.puts("2..");
|
||||
delays::wait_msec(1000);
|
||||
uart.puts(
|
||||
"3\n\
|
||||
Works!\n\n",
|
||||
);
|
||||
}
|
||||
|
||||
fn check_daif(uart: &uart::Uart) {
|
||||
uart.puts("Checking interrupt mask bits:\n");
|
||||
|
||||
let daif = DAIF.extract();
|
||||
for x in &[
|
||||
("D: ", DAIF::D),
|
||||
("A: ", DAIF::A),
|
||||
("I: ", DAIF::I),
|
||||
("F: ", DAIF::F),
|
||||
] {
|
||||
uart.puts(x.0);
|
||||
if daif.is_set(x.1) {
|
||||
uart.puts("Masked.\n");
|
||||
} else {
|
||||
uart.puts("Unmasked.\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
entry!(kernel_entry);
|
||||
|
||||
fn kernel_entry() -> ! {
|
||||
let mut mbox = mbox::Mbox::new();
|
||||
let uart = uart::Uart::new();
|
||||
|
||||
// set up serial console
|
||||
if uart.init(&mut mbox).is_err() {
|
||||
loop {
|
||||
cortex_a::asm::wfe() // If UART fails, abort early
|
||||
}
|
||||
}
|
||||
|
||||
uart.getc(); // Press a key first before being greeted
|
||||
uart.puts("Hello Rustacean!\n\n");
|
||||
|
||||
uart.puts("Executing in EL: ");
|
||||
uart.hex(CurrentEL.read(CurrentEL::EL));
|
||||
uart.puts("\n\n");
|
||||
|
||||
check_timer(&uart);
|
||||
check_daif(&uart);
|
||||
|
||||
// echo everything back
|
||||
loop {
|
||||
uart.send(uart.getc());
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,159 @@
|
||||
/*
|
||||
* MIT License
|
||||
*
|
||||
* Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
|
||||
use super::MMIO_BASE;
|
||||
use core::ops;
|
||||
use cortex_a::asm;
|
||||
use register::mmio::{ReadOnly, WriteOnly};
|
||||
|
||||
register_bitfields! {
|
||||
u32,
|
||||
|
||||
STATUS [
|
||||
FULL OFFSET(31) NUMBITS(1) [],
|
||||
EMPTY OFFSET(30) NUMBITS(1) []
|
||||
]
|
||||
}
|
||||
|
||||
const VIDEOCORE_MBOX: u32 = MMIO_BASE + 0xB880;
|
||||
|
||||
#[allow(non_snake_case)]
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
READ: ReadOnly<u32>, // 0x00
|
||||
__reserved_0: [u32; 5], // 0x04
|
||||
STATUS: ReadOnly<u32, STATUS::Register>, // 0x18
|
||||
__reserved_1: u32, // 0x1C
|
||||
WRITE: WriteOnly<u32>, // 0x20
|
||||
}
|
||||
|
||||
// Custom errors
|
||||
pub enum MboxError {
|
||||
ResponseError,
|
||||
UnknownError,
|
||||
}
|
||||
pub type Result<T> = ::core::result::Result<T, MboxError>;
|
||||
|
||||
// Channels
|
||||
pub mod channel {
|
||||
pub const PROP: u32 = 8;
|
||||
}
|
||||
|
||||
// Tags
|
||||
pub mod tag {
|
||||
pub const SETCLKRATE: u32 = 0x38002;
|
||||
pub const LAST: u32 = 0;
|
||||
}
|
||||
|
||||
// Clocks
|
||||
pub mod clock {
|
||||
pub const UART: u32 = 0x0_0000_0002;
|
||||
}
|
||||
|
||||
// Responses
|
||||
mod response {
|
||||
pub const SUCCESS: u32 = 0x8000_0000;
|
||||
pub const ERROR: u32 = 0x8000_0001; // error parsing request buffer (partial response)
|
||||
}
|
||||
|
||||
pub const REQUEST: u32 = 0;
|
||||
|
||||
// Public interface to the mailbox
|
||||
#[repr(C)]
|
||||
#[repr(align(16))]
|
||||
pub struct Mbox {
|
||||
// The address for buffer needs to be 16-byte aligned so that the
|
||||
// Videcore can handle it properly.
|
||||
pub buffer: [u32; 36],
|
||||
}
|
||||
|
||||
/// Deref to RegisterBlock
|
||||
///
|
||||
/// Allows writing
|
||||
/// ```
|
||||
/// self.STATUS.read()
|
||||
/// ```
|
||||
/// instead of something along the lines of
|
||||
/// ```
|
||||
/// unsafe { (*Mbox::ptr()).STATUS.read() }
|
||||
/// ```
|
||||
impl ops::Deref for Mbox {
|
||||
type Target = RegisterBlock;
|
||||
|
||||
fn deref(&self) -> &Self::Target {
|
||||
unsafe { &*Self::ptr() }
|
||||
}
|
||||
}
|
||||
|
||||
impl Mbox {
|
||||
pub fn new() -> Mbox {
|
||||
Mbox { buffer: [0; 36] }
|
||||
}
|
||||
|
||||
/// Returns a pointer to the register block
|
||||
fn ptr() -> *const RegisterBlock {
|
||||
VIDEOCORE_MBOX as *const _
|
||||
}
|
||||
|
||||
/// Make a mailbox call. Returns Err(MboxError) on failure, Ok(()) success
|
||||
pub fn call(&self, channel: u32) -> Result<()> {
|
||||
// wait until we can write to the mailbox
|
||||
loop {
|
||||
if !self.STATUS.is_set(STATUS::FULL) {
|
||||
break;
|
||||
}
|
||||
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
let buf_ptr = self.buffer.as_ptr() as u32;
|
||||
|
||||
// write the address of our message to the mailbox with channel identifier
|
||||
self.WRITE.set((buf_ptr & !0xF) | (channel & 0xF));
|
||||
|
||||
// now wait for the response
|
||||
loop {
|
||||
// is there a response?
|
||||
loop {
|
||||
if !self.STATUS.is_set(STATUS::EMPTY) {
|
||||
break;
|
||||
}
|
||||
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
let resp: u32 = self.READ.get();
|
||||
|
||||
// is it a response to our message?
|
||||
if ((resp & 0xF) == channel) && ((resp & !0xF) == buf_ptr) {
|
||||
// is it a valid successful response?
|
||||
return match self.buffer[1] {
|
||||
response::SUCCESS => Ok(()),
|
||||
response::ERROR => Err(MboxError::ResponseError),
|
||||
_ => Err(MboxError::UnknownError),
|
||||
};
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,286 @@
|
||||
/*
|
||||
* MIT License
|
||||
*
|
||||
* Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
|
||||
use super::MMIO_BASE;
|
||||
use core::{
|
||||
ops,
|
||||
sync::atomic::{compiler_fence, Ordering},
|
||||
};
|
||||
use cortex_a::asm;
|
||||
use gpio;
|
||||
use mbox;
|
||||
use register::mmio::*;
|
||||
|
||||
// PL011 UART registers.
|
||||
//
|
||||
// Descriptions taken from
|
||||
// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
|
||||
register_bitfields! {
|
||||
u32,
|
||||
|
||||
/// Flag Register
|
||||
FR [
|
||||
/// Transmit FIFO full. The meaning of this bit depends on the
|
||||
/// state of the FEN bit in the UARTLCR_ LCRH Register. If the
|
||||
/// FIFO is disabled, this bit is set when the transmit
|
||||
/// holding register is full. If the FIFO is enabled, the TXFF
|
||||
/// bit is set when the transmit FIFO is full.
|
||||
TXFF OFFSET(5) NUMBITS(1) [],
|
||||
|
||||
/// Receive FIFO empty. The meaning of this bit depends on the
|
||||
/// state of the FEN bit in the UARTLCR_H Register. If the
|
||||
/// FIFO is disabled, this bit is set when the receive holding
|
||||
/// register is empty. If the FIFO is enabled, the RXFE bit is
|
||||
/// set when the receive FIFO is empty.
|
||||
RXFE OFFSET(4) NUMBITS(1) []
|
||||
],
|
||||
|
||||
/// Integer Baud rate divisor
|
||||
IBRD [
|
||||
/// Integer Baud rate divisor
|
||||
IBRD OFFSET(0) NUMBITS(16) []
|
||||
],
|
||||
|
||||
/// Fractional Baud rate divisor
|
||||
FBRD [
|
||||
/// Fractional Baud rate divisor
|
||||
FBRD OFFSET(0) NUMBITS(6) []
|
||||
],
|
||||
|
||||
/// Line Control register
|
||||
LCRH [
|
||||
/// Word length. These bits indicate the number of data bits
|
||||
/// transmitted or received in a frame.
|
||||
WLEN OFFSET(5) NUMBITS(2) [
|
||||
FiveBit = 0b00,
|
||||
SixBit = 0b01,
|
||||
SevenBit = 0b10,
|
||||
EightBit = 0b11
|
||||
]
|
||||
],
|
||||
|
||||
/// Control Register
|
||||
CR [
|
||||
/// Receive enable. If this bit is set to 1, the receive
|
||||
/// section of the UART is enabled. Data reception occurs for
|
||||
/// UART signals. When the UART is disabled in the middle of
|
||||
/// reception, it completes the current character before
|
||||
/// stopping.
|
||||
RXE OFFSET(9) NUMBITS(1) [
|
||||
Disabled = 0,
|
||||
Enabled = 1
|
||||
],
|
||||
|
||||
/// Transmit enable. If this bit is set to 1, the transmit
|
||||
/// section of the UART is enabled. Data transmission occurs
|
||||
/// for UART signals. When the UART is disabled in the middle
|
||||
/// of transmission, it completes the current character before
|
||||
/// stopping.
|
||||
TXE OFFSET(8) NUMBITS(1) [
|
||||
Disabled = 0,
|
||||
Enabled = 1
|
||||
],
|
||||
|
||||
/// UART enable
|
||||
UARTEN OFFSET(0) NUMBITS(1) [
|
||||
/// If the UART is disabled in the middle of transmission
|
||||
/// or reception, it completes the current character
|
||||
/// before stopping.
|
||||
Disabled = 0,
|
||||
Enabled = 1
|
||||
]
|
||||
],
|
||||
|
||||
/// Interupt Clear Register
|
||||
ICR [
|
||||
/// Meta field for all pending interrupts
|
||||
ALL OFFSET(0) NUMBITS(11) []
|
||||
]
|
||||
}
|
||||
|
||||
const UART_BASE: u32 = MMIO_BASE + 0x20_1000;
|
||||
|
||||
#[allow(non_snake_case)]
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
DR: ReadWrite<u32>, // 0x00
|
||||
__reserved_0: [u32; 5], // 0x04
|
||||
FR: ReadOnly<u32, FR::Register>, // 0x18
|
||||
__reserved_1: [u32; 2], // 0x1c
|
||||
IBRD: WriteOnly<u32, IBRD::Register>, // 0x24
|
||||
FBRD: WriteOnly<u32, FBRD::Register>, // 0x28
|
||||
LCRH: WriteOnly<u32, LCRH::Register>, // 0x2C
|
||||
CR: WriteOnly<u32, CR::Register>, // 0x30
|
||||
__reserved_2: [u32; 4], // 0x34
|
||||
ICR: WriteOnly<u32, ICR::Register>, // 0x44
|
||||
}
|
||||
|
||||
pub enum UartError {
|
||||
MailboxError,
|
||||
}
|
||||
pub type Result<T> = ::core::result::Result<T, UartError>;
|
||||
|
||||
pub struct Uart;
|
||||
|
||||
impl ops::Deref for Uart {
|
||||
type Target = RegisterBlock;
|
||||
|
||||
fn deref(&self) -> &Self::Target {
|
||||
unsafe { &*Self::ptr() }
|
||||
}
|
||||
}
|
||||
|
||||
impl Uart {
|
||||
pub fn new() -> Uart {
|
||||
Uart
|
||||
}
|
||||
|
||||
/// Returns a pointer to the register block
|
||||
fn ptr() -> *const RegisterBlock {
|
||||
UART_BASE as *const _
|
||||
}
|
||||
|
||||
///Set baud rate and characteristics (115200 8N1) and map to GPIO
|
||||
pub fn init(&self, mbox: &mut mbox::Mbox) -> Result<()> {
|
||||
// turn off UART0
|
||||
self.CR.set(0);
|
||||
|
||||
// set up clock for consistent divisor values
|
||||
mbox.buffer[0] = 9 * 4;
|
||||
mbox.buffer[1] = mbox::REQUEST;
|
||||
mbox.buffer[2] = mbox::tag::SETCLKRATE;
|
||||
mbox.buffer[3] = 12;
|
||||
mbox.buffer[4] = 8;
|
||||
mbox.buffer[5] = mbox::clock::UART; // UART clock
|
||||
mbox.buffer[6] = 4_000_000; // 4Mhz
|
||||
mbox.buffer[7] = 0; // skip turbo setting
|
||||
mbox.buffer[8] = mbox::tag::LAST;
|
||||
|
||||
// Insert a compiler fence that ensures that all stores to the
|
||||
// mbox buffer are finished before the GPU is signaled (which
|
||||
// is done by a store operation as well).
|
||||
compiler_fence(Ordering::Release);
|
||||
|
||||
if mbox.call(mbox::channel::PROP).is_err() {
|
||||
return Err(UartError::MailboxError); // Abort if UART clocks couldn't be set
|
||||
};
|
||||
|
||||
// map UART0 to GPIO pins
|
||||
unsafe {
|
||||
(*gpio::GPFSEL1).modify(gpio::GPFSEL1::FSEL14::TXD0 + gpio::GPFSEL1::FSEL15::RXD0);
|
||||
|
||||
(*gpio::GPPUD).set(0); // enable pins 14 and 15
|
||||
for _ in 0..150 {
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
(*gpio::GPPUDCLK0).modify(
|
||||
gpio::GPPUDCLK0::PUDCLK14::AssertClock + gpio::GPPUDCLK0::PUDCLK15::AssertClock,
|
||||
);
|
||||
for _ in 0..150 {
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
(*gpio::GPPUDCLK0).set(0);
|
||||
}
|
||||
|
||||
self.ICR.write(ICR::ALL::CLEAR);
|
||||
self.IBRD.write(IBRD::IBRD.val(2)); // Results in 115200 baud
|
||||
self.FBRD.write(FBRD::FBRD.val(0xB));
|
||||
self.LCRH.write(LCRH::WLEN::EightBit); // 8N1
|
||||
self.CR
|
||||
.write(CR::UARTEN::Enabled + CR::TXE::Enabled + CR::RXE::Enabled);
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Send a character
|
||||
pub fn send(&self, c: char) {
|
||||
// wait until we can send
|
||||
loop {
|
||||
if !self.FR.is_set(FR::TXFF) {
|
||||
break;
|
||||
}
|
||||
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
// write the character to the buffer
|
||||
self.DR.set(c as u32);
|
||||
}
|
||||
|
||||
/// Receive a character
|
||||
pub fn getc(&self) -> char {
|
||||
// wait until something is in the buffer
|
||||
loop {
|
||||
if !self.FR.is_set(FR::RXFE) {
|
||||
break;
|
||||
}
|
||||
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
// read it and return
|
||||
let mut ret = self.DR.get() as u8 as char;
|
||||
|
||||
// convert carrige return to newline
|
||||
if ret == '\r' {
|
||||
ret = '\n'
|
||||
}
|
||||
|
||||
ret
|
||||
}
|
||||
|
||||
/// Display a string
|
||||
pub fn puts(&self, string: &str) {
|
||||
for c in string.chars() {
|
||||
// convert newline to carrige return + newline
|
||||
if c == '\n' {
|
||||
self.send('\r')
|
||||
}
|
||||
|
||||
self.send(c);
|
||||
}
|
||||
}
|
||||
|
||||
/// Display a binary value in hexadecimal
|
||||
pub fn hex(&self, d: u32) {
|
||||
let mut n;
|
||||
|
||||
for i in 0..8 {
|
||||
// get highest tetrad
|
||||
n = d.wrapping_shr(28 - i * 4) & 0xF;
|
||||
|
||||
// 0-9 => '0'-'9', 10-15 => 'A'-'F'
|
||||
// Add proper offset for ASCII table
|
||||
if n > 9 {
|
||||
n += 0x37;
|
||||
} else {
|
||||
n += 0x30;
|
||||
}
|
||||
|
||||
self.send(n as u8 as char);
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue