Add code for tutorial 06
Andre Richter
5 years ago
parent
4ac92b45dc
commit
6cfd5ccada
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newline_style = "Unix"
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edition = "2018"
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format_code_in_doc_comments = true
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@ -0,0 +1,4 @@
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{
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"rust.features": ["bsp_rpi3"],
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"rust.all_targets": false,
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}
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@ -0,0 +1,42 @@
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# This file is automatically @generated by Cargo.
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# It is not intended for manual editing.
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[[package]]
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name = "cortex-a"
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version = "2.7.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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"register 0.3.3 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "kernel"
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version = "0.1.0"
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dependencies = [
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"cortex-a 2.7.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"register 0.3.3 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "r0"
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version = "0.2.2"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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name = "register"
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version = "0.3.3"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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"tock-registers 0.3.0 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "tock-registers"
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version = "0.3.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[metadata]
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"checksum cortex-a 2.7.0 (registry+https://github.com/rust-lang/crates.io-index)" = "cbb16c411ab74044f174746a6cbae67bcdebea126e376b5441e5986e6a6aa950"
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"checksum r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)" = "e2a38df5b15c8d5c7e8654189744d8e396bddc18ad48041a500ce52d6948941f"
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"checksum register 0.3.3 (registry+https://github.com/rust-lang/crates.io-index)" = "469bb5ddde81d67fb8bba4e14d77689b8166cfd077abe7530591cefe29d05823"
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"checksum tock-registers 0.3.0 (registry+https://github.com/rust-lang/crates.io-index)" = "c758f5195a2e0df9d9fecf6f506506b2766ff74cf64db1e995c87e2761a5c3e2"
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@ -0,0 +1,20 @@
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[package]
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name = "kernel"
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version = "0.1.0"
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authors = ["Andre Richter <andre.o.richter@gmail.com>"]
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edition = "2018"
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[package.metadata.cargo-xbuild]
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sysroot_path = "../xbuild_sysroot"
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# The features section is used to select the target board.
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[features]
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default = []
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bsp_rpi3 = ["cortex-a", "register"]
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[dependencies]
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r0 = "0.2.*"
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# Optional dependencies
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cortex-a = { version = "2.*", optional = true }
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register = { version = "0.3.*", optional = true }
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@ -0,0 +1,76 @@
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## SPDX-License-Identifier: MIT
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##
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## Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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# Default to the RPi3
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ifndef BSP
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BSP = bsp_rpi3
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endif
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# BSP-specific arguments
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ifeq ($(BSP),bsp_rpi3)
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TARGET = aarch64-unknown-none-softfloat
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OUTPUT = kernel8.img
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QEMU_BINARY = qemu-system-aarch64
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QEMU_MACHINE_TYPE = raspi3
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QEMU_MISC_ARGS = -serial null -serial stdio
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LINKER_FILE = src/bsp/rpi3/link.ld
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RUSTC_MISC_ARGS = -C target-cpu=cortex-a53
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endif
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SOURCES = $(wildcard **/*.rs) $(wildcard **/*.S) $(wildcard **/*.ld)
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XRUSTC_CMD = cargo xrustc \
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--target=$(TARGET) \
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--features $(BSP) \
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--release \
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-- \
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-C link-arg=-T$(LINKER_FILE) \
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$(RUSTC_MISC_ARGS)
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CARGO_OUTPUT = target/$(TARGET)/release/kernel
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OBJCOPY_CMD = cargo objcopy \
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-- \
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--strip-all \
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-O binary
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CONTAINER_UTILS = rustembedded/osdev-utils
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DOCKER_CMD = docker run -it --rm
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DOCKER_ARG_CURDIR = -v $(shell pwd):/work -w /work
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DOCKER_EXEC_QEMU = $(QEMU_BINARY) -M $(QEMU_MACHINE_TYPE) -kernel $(OUTPUT)
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.PHONY: all qemu clippy clean readelf objdump nm
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all: clean $(OUTPUT)
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$(CARGO_OUTPUT): $(SOURCES)
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RUSTFLAGS="-D warnings -D missing_docs" $(XRUSTC_CMD)
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$(OUTPUT): $(CARGO_OUTPUT)
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cp $< .
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$(OBJCOPY_CMD) $< $(OUTPUT)
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doc:
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cargo xdoc --target=$(TARGET) --features $(BSP) --document-private-items
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xdg-open target/$(TARGET)/doc/kernel/index.html
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qemu: all
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$(DOCKER_CMD) $(DOCKER_ARG_CURDIR) $(CONTAINER_UTILS) \
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$(DOCKER_EXEC_QEMU) $(QEMU_MISC_ARGS)
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clippy:
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cargo xclippy --target=$(TARGET) --features $(BSP)
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clean:
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cargo clean
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readelf:
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readelf -a kernel
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objdump:
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cargo objdump --target $(TARGET) -- -disassemble -print-imm-hex kernel
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nm:
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cargo nm --target $(TARGET) -- kernel | sort
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@ -0,0 +1,711 @@
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# Tutorial 06 - Drivers: GPIO and UART
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## tl;dr
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Now that we enabled safe globals in the previous tutorial, the infrastructure is
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laid for adding the first real device drivers. We throw out the magic QEMU
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console and use a real UART now. Like real though embedded people do!
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- A `DeviceDriver` trait is added for abstracting BSP driver implementations
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from kernel code.
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- Introducing the `GPIO` driver, which pinmuxes the RPi's Mini UART.
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- Most importantly, the `MiniUart` driver: It implements the `Console` traits
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and is from now on used as the system console output.
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- **Be sure to check it out by booting this kernel from the SD card and
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watching the output!**
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- `memory_map.rs` contains the RPi3 device's MMIO addresses.
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## Diff to previous
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```diff
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diff -uNr 05_safe_globals/Cargo.toml 06_drivers_gpio_uart/Cargo.toml
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--- 05_safe_globals/Cargo.toml
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+++ 06_drivers_gpio_uart/Cargo.toml
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@@ -10,10 +10,11 @@
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# The features section is used to select the target board.
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[features]
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default = []
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-bsp_rpi3 = ["cortex-a"]
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+bsp_rpi3 = ["cortex-a", "register"]
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[dependencies]
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r0 = "0.2.*"
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# Optional dependencies
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cortex-a = { version = "2.*", optional = true }
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+register = { version = "0.3.*", optional = true }
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diff -uNr 05_safe_globals/src/bsp/rpi3/driver/gpio.rs 06_drivers_gpio_uart/src/bsp/rpi3/driver/gpio.rs
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--- 05_safe_globals/src/bsp/rpi3/driver/gpio.rs
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+++ 06_drivers_gpio_uart/src/bsp/rpi3/driver/gpio.rs
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@@ -0,0 +1,164 @@
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+// SPDX-License-Identifier: MIT
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+//
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+// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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+
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+//! GPIO driver.
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+
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+use super::super::NullLock;
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+use crate::interface;
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+use core::ops;
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+use cortex_a::asm;
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+use register::{mmio::ReadWrite, register_bitfields};
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+
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+// GPIO registers.
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+//
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+// Descriptions taken from
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+// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
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+register_bitfields! {
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+ u32,
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+
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+ /// GPIO Function Select 1
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+ GPFSEL1 [
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+ /// Pin 15
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+ FSEL15 OFFSET(15) NUMBITS(3) [
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+ Input = 0b000,
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+ Output = 0b001,
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+ RXD0 = 0b100, // UART0 - Alternate function 0
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+ RXD1 = 0b010 // Mini UART - Alternate function 5
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+
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+ ],
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+
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+ /// Pin 14
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+ FSEL14 OFFSET(12) NUMBITS(3) [
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+ Input = 0b000,
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+ Output = 0b001,
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+ TXD0 = 0b100, // UART0 - Alternate function 0
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+ TXD1 = 0b010 // Mini UART - Alternate function 5
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+ ]
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+ ],
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+
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+ /// GPIO Pull-up/down Clock Register 0
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+ GPPUDCLK0 [
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+ /// Pin 15
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+ PUDCLK15 OFFSET(15) NUMBITS(1) [
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+ NoEffect = 0,
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+ AssertClock = 1
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+ ],
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+
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+ /// Pin 14
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+ PUDCLK14 OFFSET(14) NUMBITS(1) [
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+ NoEffect = 0,
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+ AssertClock = 1
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+ ]
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+ ]
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+}
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+
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+#[allow(non_snake_case)]
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+#[repr(C)]
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+pub struct RegisterBlock {
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+ pub GPFSEL0: ReadWrite<u32>, // 0x00
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+ pub GPFSEL1: ReadWrite<u32, GPFSEL1::Register>, // 0x04
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+ pub GPFSEL2: ReadWrite<u32>, // 0x08
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+ pub GPFSEL3: ReadWrite<u32>, // 0x0C
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+ pub GPFSEL4: ReadWrite<u32>, // 0x10
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+ pub GPFSEL5: ReadWrite<u32>, // 0x14
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+ __reserved_0: u32, // 0x18
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+ GPSET0: ReadWrite<u32>, // 0x1C
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+ GPSET1: ReadWrite<u32>, // 0x20
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+ __reserved_1: u32, //
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+ GPCLR0: ReadWrite<u32>, // 0x28
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+ __reserved_2: [u32; 2], //
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+ GPLEV0: ReadWrite<u32>, // 0x34
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+ GPLEV1: ReadWrite<u32>, // 0x38
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+ __reserved_3: u32, //
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+ GPEDS0: ReadWrite<u32>, // 0x40
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+ GPEDS1: ReadWrite<u32>, // 0x44
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+ __reserved_4: [u32; 7], //
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+ GPHEN0: ReadWrite<u32>, // 0x64
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+ GPHEN1: ReadWrite<u32>, // 0x68
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+ __reserved_5: [u32; 10], //
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+ pub GPPUD: ReadWrite<u32>, // 0x94
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+ pub GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>, // 0x98
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+ pub GPPUDCLK1: ReadWrite<u32>, // 0x9C
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+}
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+
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+/// The driver's private data.
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+struct GPIOInner {
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+ base_addr: usize,
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+}
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+
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+/// Deref to RegisterBlock.
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+impl ops::Deref for GPIOInner {
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+ type Target = RegisterBlock;
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+
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+ fn deref(&self) -> &Self::Target {
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+ unsafe { &*self.ptr() }
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+ }
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+}
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+
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+impl GPIOInner {
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+ const fn new(base_addr: usize) -> GPIOInner {
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+ GPIOInner { base_addr }
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+ }
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+
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+ /// Return a pointer to the register block.
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+ fn ptr(&self) -> *const RegisterBlock {
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+ self.base_addr as *const _
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+ }
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+
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+ /// Map Mini UART as standard output.
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+ ///
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+ /// TX to pin 14
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+ /// RX to pin 15
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+ fn map_mini_uart(&mut self) {
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+ // Map to pins.
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+ self.GPFSEL1
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+ .modify(GPFSEL1::FSEL14::TXD1 + GPFSEL1::FSEL15::RXD1);
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+
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+ // Enable pins 14 and 15.
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+ self.GPPUD.set(0);
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+ for _ in 0..150 {
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+ asm::nop();
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+ }
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+
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+ self.GPPUDCLK0
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+ .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
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+ for _ in 0..150 {
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+ asm::nop();
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+ }
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+
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+ self.GPPUDCLK0.set(0);
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+ }
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+}
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+
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+////////////////////////////////////////////////////////////////////////////////
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+// OS interface implementations
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+////////////////////////////////////////////////////////////////////////////////
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+
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+/// The driver's public data.
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+pub struct GPIO {
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+ inner: NullLock<GPIOInner>,
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+}
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+
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+impl GPIO {
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+ pub const unsafe fn new(base_addr: usize) -> GPIO {
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+ GPIO {
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+ inner: NullLock::new(GPIOInner::new(base_addr)),
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+ }
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+ }
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+}
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+
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+impl interface::driver::DeviceDriver for GPIO {
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+ fn compatible(&self) -> &str {
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+ "GPIO"
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+ }
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+
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+ fn init(&self) -> interface::driver::Result {
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+ use interface::sync::Mutex;
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+
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+ let mut r = &self.inner;
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+ r.lock(|i| i.map_mini_uart());
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+
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+ Ok(())
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+ }
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+}
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diff -uNr 05_safe_globals/src/bsp/rpi3/driver/mini_uart.rs 06_drivers_gpio_uart/src/bsp/rpi3/driver/mini_uart.rs
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--- 05_safe_globals/src/bsp/rpi3/driver/mini_uart.rs
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+++ 06_drivers_gpio_uart/src/bsp/rpi3/driver/mini_uart.rs
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@@ -0,0 +1,263 @@
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+// SPDX-License-Identifier: MIT
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+//
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+// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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+
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+//! Mini UART driver.
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+
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+use super::super::NullLock;
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+use crate::interface;
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+use core::{fmt, ops};
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+use cortex_a::asm;
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+use register::{mmio::*, register_bitfields};
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+
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+// Mini UART registers.
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+//
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+// Descriptions taken from
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+// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
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+register_bitfields! {
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+ u32,
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+
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+ /// Auxiliary enables
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+ AUX_ENABLES [
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+ /// If set the mini UART is enabled. The UART will immediately
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+ /// start receiving data, especially if the UART1_RX line is
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+ /// low.
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+ /// If clear the mini UART is disabled. That also disables any
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+ /// mini UART register access
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+ MINI_UART_ENABLE OFFSET(0) NUMBITS(1) []
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+ ],
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+
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+ /// Mini Uart Interrupt Identify
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+ AUX_MU_IIR [
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+ /// Writing with bit 1 set will clear the receive FIFO
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+ /// Writing with bit 2 set will clear the transmit FIFO
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+ FIFO_CLEAR OFFSET(1) NUMBITS(2) [
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+ Rx = 0b01,
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+ Tx = 0b10,
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+ All = 0b11
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+ ]
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+ ],
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+
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+ /// Mini Uart Line Control
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+ AUX_MU_LCR [
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+ /// Mode the UART works in
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+ DATA_SIZE OFFSET(0) NUMBITS(2) [
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+ SevenBit = 0b00,
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+ EightBit = 0b11
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+ ]
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+ ],
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+
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+ /// Mini Uart Line Status
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+ AUX_MU_LSR [
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+ /// This bit is set if the transmit FIFO is empty and the transmitter is
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+ /// idle. (Finished shifting out the last bit).
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+ TX_IDLE OFFSET(6) NUMBITS(1) [],
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+
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+ /// This bit is set if the transmit FIFO can accept at least
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+ /// one byte.
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+ TX_EMPTY OFFSET(5) NUMBITS(1) [],
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+
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+ /// This bit is set if the receive FIFO holds at least 1
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+ /// symbol.
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+ DATA_READY OFFSET(0) NUMBITS(1) []
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+ ],
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+
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+ /// Mini Uart Extra Control
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+ AUX_MU_CNTL [
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+ /// If this bit is set the mini UART transmitter is enabled.
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+ /// If this bit is clear the mini UART transmitter is disabled.
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+ TX_EN OFFSET(1) NUMBITS(1) [
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+ Disabled = 0,
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+ Enabled = 1
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+ ],
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+
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+ /// If this bit is set the mini UART receiver is enabled.
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+ /// If this bit is clear the mini UART receiver is disabled.
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+ RX_EN OFFSET(0) NUMBITS(1) [
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+ Disabled = 0,
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+ Enabled = 1
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+ ]
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+ ],
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+
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+ /// Mini Uart Baudrate
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+ AUX_MU_BAUD [
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+ /// Mini UART baudrate counter
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+ RATE OFFSET(0) NUMBITS(16) []
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+ ]
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+}
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+
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+#[allow(non_snake_case)]
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+#[repr(C)]
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+pub struct RegisterBlock {
|
||||
+ __reserved_0: u32, // 0x00
|
||||
+ AUX_ENABLES: ReadWrite<u32, AUX_ENABLES::Register>, // 0x04
|
||||
+ __reserved_1: [u32; 14], // 0x08
|
||||
+ AUX_MU_IO: ReadWrite<u32>, // 0x40 - Mini Uart I/O Data
|
||||
+ AUX_MU_IER: WriteOnly<u32>, // 0x44 - Mini Uart Interrupt Enable
|
||||
+ AUX_MU_IIR: WriteOnly<u32, AUX_MU_IIR::Register>, // 0x48
|
||||
+ AUX_MU_LCR: WriteOnly<u32, AUX_MU_LCR::Register>, // 0x4C
|
||||
+ AUX_MU_MCR: WriteOnly<u32>, // 0x50
|
||||
+ AUX_MU_LSR: ReadOnly<u32, AUX_MU_LSR::Register>, // 0x54
|
||||
+ __reserved_2: [u32; 2], // 0x58
|
||||
+ AUX_MU_CNTL: WriteOnly<u32, AUX_MU_CNTL::Register>, // 0x60
|
||||
+ __reserved_3: u32, // 0x64
|
||||
+ AUX_MU_BAUD: WriteOnly<u32, AUX_MU_BAUD::Register>, // 0x68
|
||||
+}
|
||||
+
|
||||
+/// The driver's mutex protected part.
|
||||
+struct MiniUartInner {
|
||||
+ base_addr: usize,
|
||||
+ chars_written: usize,
|
||||
+}
|
||||
+
|
||||
+/// Deref to RegisterBlock.
|
||||
+///
|
||||
+/// Allows writing
|
||||
+/// ```
|
||||
+/// self.MU_IER.read()
|
||||
+/// ```
|
||||
+/// instead of something along the lines of
|
||||
+/// ```
|
||||
+/// unsafe { (*MiniUart::ptr()).MU_IER.read() }
|
||||
+/// ```
|
||||
+impl ops::Deref for MiniUartInner {
|
||||
+ type Target = RegisterBlock;
|
||||
+
|
||||
+ fn deref(&self) -> &Self::Target {
|
||||
+ unsafe { &*self.ptr() }
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+impl MiniUartInner {
|
||||
+ const fn new(base_addr: usize) -> MiniUartInner {
|
||||
+ MiniUartInner {
|
||||
+ base_addr,
|
||||
+ chars_written: 0,
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /// Return a pointer to the register block.
|
||||
+ fn ptr(&self) -> *const RegisterBlock {
|
||||
+ self.base_addr as *const _
|
||||
+ }
|
||||
+
|
||||
+ /// Set up baud rate and characteristics (115200 8N1).
|
||||
+ fn init(&mut self) -> interface::driver::Result {
|
||||
+ self.AUX_ENABLES.modify(AUX_ENABLES::MINI_UART_ENABLE::SET);
|
||||
+ self.AUX_MU_IER.set(0);
|
||||
+ self.AUX_MU_CNTL.set(0);
|
||||
+ self.AUX_MU_LCR.write(AUX_MU_LCR::DATA_SIZE::EightBit);
|
||||
+ self.AUX_MU_MCR.set(0);
|
||||
+ self.AUX_MU_IER.set(0);
|
||||
+ self.AUX_MU_IIR.write(AUX_MU_IIR::FIFO_CLEAR::All);
|
||||
+ self.AUX_MU_BAUD.write(AUX_MU_BAUD::RATE.val(270)); // 115200 baud
|
||||
+
|
||||
+ // Enable receive and send.
|
||||
+ self.AUX_MU_CNTL
|
||||
+ .write(AUX_MU_CNTL::RX_EN::Enabled + AUX_MU_CNTL::TX_EN::Enabled);
|
||||
+
|
||||
+ // Clear FIFOs before using the device.
|
||||
+ self.AUX_MU_IIR.write(AUX_MU_IIR::FIFO_CLEAR::All);
|
||||
+
|
||||
+ Ok(())
|
||||
+ }
|
||||
+
|
||||
+ /// Send a character.
|
||||
+ fn write_char(&mut self, c: char) {
|
||||
+ // Wait until we can send.
|
||||
+ loop {
|
||||
+ if self.AUX_MU_LSR.is_set(AUX_MU_LSR::TX_EMPTY) {
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ asm::nop();
|
||||
+ }
|
||||
+
|
||||
+ // Write the character to the buffer.
|
||||
+ self.AUX_MU_IO.set(c as u32);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+/// Implementing `core::fmt::Write` enables usage of the `format_args!` macros,
|
||||
+/// which in turn are used to implement the `kernel`'s `print!` and `println!`
|
||||
+/// macros. By implementing `write_str()`, we get `write_fmt()` automatically.
|
||||
+///
|
||||
+/// The function takes an `&mut self`, so it must be implemented for the inner
|
||||
+/// struct.
|
||||
+///
|
||||
+/// See [`src/print.rs`].
|
||||
+///
|
||||
+/// [`src/print.rs`]: ../../print/index.html
|
||||
+impl fmt::Write for MiniUartInner {
|
||||
+ fn write_str(&mut self, s: &str) -> fmt::Result {
|
||||
+ for c in s.chars() {
|
||||
+ // Convert newline to carrige return + newline.
|
||||
+ if c == '
|
||||
' {
|
||||
+ self.write_char('
|
||||
')
|
||||
+ }
|
||||
+
|
||||
+ self.write_char(c);
|
||||
+ }
|
||||
+
|
||||
+ self.chars_written += s.len();
|
||||
+
|
||||
+ Ok(())
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+////////////////////////////////////////////////////////////////////////////////
|
||||
+// OS interface implementations
|
||||
+////////////////////////////////////////////////////////////////////////////////
|
||||
+
|
||||
+/// The driver's main struct.
|
||||
+pub struct MiniUart {
|
||||
+ inner: NullLock<MiniUartInner>,
|
||||
+}
|
||||
+
|
||||
+impl MiniUart {
|
||||
+ /// # Safety
|
||||
+ ///
|
||||
+ /// The user must ensure to provide the correct `base_addr`.
|
||||
+ pub const unsafe fn new(base_addr: usize) -> MiniUart {
|
||||
+ MiniUart {
|
||||
+ inner: NullLock::new(MiniUartInner::new(base_addr)),
|
||||
+ }
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+impl interface::driver::DeviceDriver for MiniUart {
|
||||
+ fn compatible(&self) -> &str {
|
||||
+ "MiniUart"
|
||||
+ }
|
||||
+
|
||||
+ fn init(&self) -> interface::driver::Result {
|
||||
+ use interface::sync::Mutex;
|
||||
+
|
||||
+ let mut r = &self.inner;
|
||||
+ r.lock(|i| i.init())
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+/// Passthrough of `args` to the `core::fmt::Write` implementation, but guarded
|
||||
+/// by a Mutex to serialize access.
|
||||
+impl interface::console::Write for MiniUart {
|
||||
+ fn write_fmt(&self, args: core::fmt::Arguments) -> fmt::Result {
|
||||
+ use interface::sync::Mutex;
|
||||
+
|
||||
+ // Fully qualified syntax for the call to
|
||||
+ // `core::fmt::Write::write:fmt()` to increase readability.
|
||||
+ let mut r = &self.inner;
|
||||
+ r.lock(|i| fmt::Write::write_fmt(i, args))
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+impl interface::console::Read for MiniUart {}
|
||||
+
|
||||
+impl interface::console::Statistics for MiniUart {
|
||||
+ fn chars_written(&self) -> usize {
|
||||
+ use interface::sync::Mutex;
|
||||
+
|
||||
+ let mut r = &self.inner;
|
||||
+ r.lock(|i| i.chars_written)
|
||||
+ }
|
||||
+}
|
||||
|
||||
diff -uNr 05_safe_globals/src/bsp/rpi3/driver.rs 06_drivers_gpio_uart/src/bsp/rpi3/driver.rs
|
||||
--- 05_safe_globals/src/bsp/rpi3/driver.rs
|
||||
+++ 06_drivers_gpio_uart/src/bsp/rpi3/driver.rs
|
||||
@@ -0,0 +1,11 @@
|
||||
+// SPDX-License-Identifier: MIT
|
||||
+//
|
||||
+// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
+
|
||||
+//! Collection of device drivers.
|
||||
+
|
||||
+mod gpio;
|
||||
+mod mini_uart;
|
||||
+
|
||||
+pub use gpio::GPIO;
|
||||
+pub use mini_uart::MiniUart;
|
||||
|
||||
diff -uNr 05_safe_globals/src/bsp/rpi3/memory_map.rs 06_drivers_gpio_uart/src/bsp/rpi3/memory_map.rs
|
||||
--- 05_safe_globals/src/bsp/rpi3/memory_map.rs
|
||||
+++ 06_drivers_gpio_uart/src/bsp/rpi3/memory_map.rs
|
||||
@@ -0,0 +1,13 @@
|
||||
+// SPDX-License-Identifier: MIT
|
||||
+//
|
||||
+// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
+
|
||||
+//! The board's memory map.
|
||||
+
|
||||
+/// Physical devices.
|
||||
+#[rustfmt::skip]
|
||||
+pub mod mmio {
|
||||
+ pub const BASE: usize = 0x3F00_0000;
|
||||
+ pub const GPIO_BASE: usize = BASE + 0x0020_0000;
|
||||
+ pub const MINI_UART_BASE: usize = BASE + 0x0021_5000;
|
||||
+}
|
||||
|
||||
diff -uNr 05_safe_globals/src/bsp/rpi3.rs 06_drivers_gpio_uart/src/bsp/rpi3.rs
|
||||
--- 05_safe_globals/src/bsp/rpi3.rs
|
||||
+++ 06_drivers_gpio_uart/src/bsp/rpi3.rs
|
||||
@@ -4,11 +4,12 @@
|
||||
|
||||
//! Board Support Package for the Raspberry Pi 3.
|
||||
|
||||
+mod driver;
|
||||
+mod memory_map;
|
||||
mod panic_wait;
|
||||
mod sync;
|
||||
|
||||
use crate::interface;
|
||||
-use core::fmt;
|
||||
use cortex_a::{asm, regs::*};
|
||||
use sync::NullLock;
|
||||
|
||||
@@ -39,99 +40,13 @@
|
||||
}
|
||||
}
|
||||
|
||||
-/// A mystical, magical device for generating QEMU output out of the void.
|
||||
-///
|
||||
-/// The mutex protected part.
|
||||
-struct QEMUOutputInner {
|
||||
- chars_written: usize,
|
||||
-}
|
||||
-
|
||||
-impl QEMUOutputInner {
|
||||
- const fn new() -> QEMUOutputInner {
|
||||
- QEMUOutputInner { chars_written: 0 }
|
||||
- }
|
||||
-
|
||||
- /// Send a character.
|
||||
- fn write_char(&mut self, c: char) {
|
||||
- unsafe {
|
||||
- core::ptr::write_volatile(0x3F21_5040 as *mut u8, c as u8);
|
||||
- }
|
||||
- }
|
||||
-}
|
||||
-
|
||||
-/// Implementing `core::fmt::Write` enables usage of the `format_args!` macros,
|
||||
-/// which in turn are used to implement the `kernel`'s `print!` and `println!`
|
||||
-/// macros. By implementing `write_str()`, we get `write_fmt()` automatically.
|
||||
-///
|
||||
-/// The function takes an `&mut self`, so it must be implemented for the inner
|
||||
-/// struct.
|
||||
-///
|
||||
-/// See [`src/print.rs`].
|
||||
-///
|
||||
-/// [`src/print.rs`]: ../../print/index.html
|
||||
-impl fmt::Write for QEMUOutputInner {
|
||||
- fn write_str(&mut self, s: &str) -> fmt::Result {
|
||||
- for c in s.chars() {
|
||||
- // Convert newline to carrige return + newline.
|
||||
- if c == '
|
||||
' {
|
||||
- self.write_char('
|
||||
')
|
||||
- }
|
||||
-
|
||||
- self.write_char(c);
|
||||
- }
|
||||
-
|
||||
- self.chars_written += s.len();
|
||||
-
|
||||
- Ok(())
|
||||
- }
|
||||
-}
|
||||
-
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
-// OS interface implementations
|
||||
+// Global BSP driver instances
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
-/// The main struct.
|
||||
-pub struct QEMUOutput {
|
||||
- inner: NullLock<QEMUOutputInner>,
|
||||
-}
|
||||
-
|
||||
-impl QEMUOutput {
|
||||
- pub const fn new() -> QEMUOutput {
|
||||
- QEMUOutput {
|
||||
- inner: NullLock::new(QEMUOutputInner::new()),
|
||||
- }
|
||||
- }
|
||||
-}
|
||||
-
|
||||
-/// Passthrough of `args` to the `core::fmt::Write` implementation, but guarded
|
||||
-/// by a Mutex to serialize access.
|
||||
-impl interface::console::Write for QEMUOutput {
|
||||
- fn write_fmt(&self, args: core::fmt::Arguments) -> fmt::Result {
|
||||
- use interface::sync::Mutex;
|
||||
-
|
||||
- // Fully qualified syntax for the call to
|
||||
- // `core::fmt::Write::write:fmt()` to increase readability.
|
||||
- let mut r = &self.inner;
|
||||
- r.lock(|i| fmt::Write::write_fmt(i, args))
|
||||
- }
|
||||
-}
|
||||
-
|
||||
-impl interface::console::Read for QEMUOutput {}
|
||||
-
|
||||
-impl interface::console::Statistics for QEMUOutput {
|
||||
- fn chars_written(&self) -> usize {
|
||||
- use interface::sync::Mutex;
|
||||
-
|
||||
- let mut r = &self.inner;
|
||||
- r.lock(|i| i.chars_written)
|
||||
- }
|
||||
-}
|
||||
-
|
||||
-////////////////////////////////////////////////////////////////////////////////
|
||||
-// Global instances
|
||||
-////////////////////////////////////////////////////////////////////////////////
|
||||
-
|
||||
-static QEMU_OUTPUT: QEMUOutput = QEMUOutput::new();
|
||||
+static GPIO: driver::GPIO = unsafe { driver::GPIO::new(memory_map::mmio::GPIO_BASE) };
|
||||
+static MINI_UART: driver::MiniUart =
|
||||
+ unsafe { driver::MiniUart::new(memory_map::mmio::MINI_UART_BASE) };
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Implementation of the kernel's BSP calls
|
||||
@@ -146,5 +61,15 @@
|
||||
|
||||
/// Return a reference to a `console::All` implementation.
|
||||
pub fn console() -> &'static impl interface::console::All {
|
||||
- &QEMU_OUTPUT
|
||||
+ &MINI_UART
|
||||
+}
|
||||
+
|
||||
+/// Return an array of references to all `DeviceDriver` compatible `BSP`
|
||||
+/// drivers.
|
||||
+///
|
||||
+/// # Safety
|
||||
+///
|
||||
+/// The order of devices is the order in which `DeviceDriver::init()` is called.
|
||||
+pub fn device_drivers() -> [&'static dyn interface::driver::DeviceDriver; 2] {
|
||||
+ [&GPIO, &MINI_UART]
|
||||
}
|
||||
|
||||
diff -uNr 05_safe_globals/src/interface.rs 06_drivers_gpio_uart/src/interface.rs
|
||||
--- 05_safe_globals/src/interface.rs
|
||||
+++ 06_drivers_gpio_uart/src/interface.rs
|
||||
@@ -85,3 +85,20 @@
|
||||
fn lock<R>(&mut self, f: impl FnOnce(&mut Self::Data) -> R) -> R;
|
||||
}
|
||||
}
|
||||
+
|
||||
+/// Driver interfaces.
|
||||
+pub mod driver {
|
||||
+ /// Driver result type, e.g. for indicating successful driver init.
|
||||
+ pub type Result = core::result::Result<(), ()>;
|
||||
+
|
||||
+ /// Device Driver operations.
|
||||
+ pub trait DeviceDriver {
|
||||
+ /// Return a compatibility string for identifying the driver.
|
||||
+ fn compatible(&self) -> &str;
|
||||
+
|
||||
+ /// Called by the kernel to bring up the device.
|
||||
+ fn init(&self) -> Result {
|
||||
+ Ok(())
|
||||
+ }
|
||||
+ }
|
||||
+}
|
||||
|
||||
diff -uNr 05_safe_globals/src/main.rs 06_drivers_gpio_uart/src/main.rs
|
||||
--- 05_safe_globals/src/main.rs
|
||||
+++ 06_drivers_gpio_uart/src/main.rs
|
||||
@@ -34,10 +34,27 @@
|
||||
fn kernel_entry() -> ! {
|
||||
use interface::console::Statistics;
|
||||
|
||||
+ // Initialize the BSP's device drivers.
|
||||
+ for i in bsp::device_drivers().iter() {
|
||||
+ if let Err(()) = i.init() {
|
||||
+ // This message will only be readable if, at the time of failure,
|
||||
+ // the return value of `bsp::console()` is already in functioning
|
||||
+ // state.
|
||||
+ panic!("Error loading driver: {}", i.compatible())
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ // If all drivers are loaded, UART is functional now and `println!()` calls
|
||||
+ // are transmitted on the physical wires.
|
||||
println!("[0] Hello from pure Rust!");
|
||||
|
||||
- println!("[1] Chars written: {}", bsp::console().chars_written());
|
||||
+ println!("[1] Drivers probed:");
|
||||
+ for (i, driver) in bsp::device_drivers().iter().enumerate() {
|
||||
+ println!(" {}. {}", i + 1, driver.compatible());
|
||||
+ }
|
||||
+
|
||||
+ println!("[2] Chars written: {}", bsp::console().chars_written());
|
||||
|
||||
- println!("[2] Stopping here.");
|
||||
+ println!("[3] Stopping here.");
|
||||
bsp::wait_forever()
|
||||
}
|
||||
```
|
||||
Binary file not shown.
Binary file not shown.
@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! Conditional exporting of Board Support Packages.
|
||||
|
||||
#[cfg(feature = "bsp_rpi3")]
|
||||
pub mod rpi3;
|
||||
|
||||
#[cfg(feature = "bsp_rpi3")]
|
||||
pub use rpi3::*;
|
||||
@ -0,0 +1,75 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! Board Support Package for the Raspberry Pi 3.
|
||||
|
||||
mod driver;
|
||||
mod memory_map;
|
||||
mod panic_wait;
|
||||
mod sync;
|
||||
|
||||
use crate::interface;
|
||||
use cortex_a::{asm, regs::*};
|
||||
use sync::NullLock;
|
||||
|
||||
/// The entry of the `kernel` binary.
|
||||
///
|
||||
/// The function must be named `_start`, because the linker is looking for this
|
||||
/// exact name.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// - Linker script must ensure to place this function at `0x80_000`.
|
||||
#[no_mangle]
|
||||
pub unsafe extern "C" fn _start() -> ! {
|
||||
use crate::runtime_init;
|
||||
|
||||
const CORE_0: u64 = 0;
|
||||
const CORE_MASK: u64 = 0x3;
|
||||
const STACK_START: u64 = 0x80_000;
|
||||
|
||||
if CORE_0 == MPIDR_EL1.get() & CORE_MASK {
|
||||
SP.set(STACK_START);
|
||||
runtime_init::init()
|
||||
} else {
|
||||
// if not core0, infinitely wait for events
|
||||
loop {
|
||||
asm::wfe();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Global BSP driver instances
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
static GPIO: driver::GPIO = unsafe { driver::GPIO::new(memory_map::mmio::GPIO_BASE) };
|
||||
static MINI_UART: driver::MiniUart =
|
||||
unsafe { driver::MiniUart::new(memory_map::mmio::MINI_UART_BASE) };
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Implementation of the kernel's BSP calls
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/// Park execution on the calling CPU core.
|
||||
pub fn wait_forever() -> ! {
|
||||
loop {
|
||||
asm::wfe()
|
||||
}
|
||||
}
|
||||
|
||||
/// Return a reference to a `console::All` implementation.
|
||||
pub fn console() -> &'static impl interface::console::All {
|
||||
&MINI_UART
|
||||
}
|
||||
|
||||
/// Return an array of references to all `DeviceDriver` compatible `BSP`
|
||||
/// drivers.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// The order of devices is the order in which `DeviceDriver::init()` is called.
|
||||
pub fn device_drivers() -> [&'static dyn interface::driver::DeviceDriver; 2] {
|
||||
[&GPIO, &MINI_UART]
|
||||
}
|
||||
@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! Collection of device drivers.
|
||||
|
||||
mod gpio;
|
||||
mod mini_uart;
|
||||
|
||||
pub use gpio::GPIO;
|
||||
pub use mini_uart::MiniUart;
|
||||
@ -0,0 +1,164 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! GPIO driver.
|
||||
|
||||
use super::super::NullLock;
|
||||
use crate::interface;
|
||||
use core::ops;
|
||||
use cortex_a::asm;
|
||||
use register::{mmio::ReadWrite, register_bitfields};
|
||||
|
||||
// GPIO registers.
|
||||
//
|
||||
// Descriptions taken from
|
||||
// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
|
||||
register_bitfields! {
|
||||
u32,
|
||||
|
||||
/// GPIO Function Select 1
|
||||
GPFSEL1 [
|
||||
/// Pin 15
|
||||
FSEL15 OFFSET(15) NUMBITS(3) [
|
||||
Input = 0b000,
|
||||
Output = 0b001,
|
||||
RXD0 = 0b100, // UART0 - Alternate function 0
|
||||
RXD1 = 0b010 // Mini UART - Alternate function 5
|
||||
|
||||
],
|
||||
|
||||
/// Pin 14
|
||||
FSEL14 OFFSET(12) NUMBITS(3) [
|
||||
Input = 0b000,
|
||||
Output = 0b001,
|
||||
TXD0 = 0b100, // UART0 - Alternate function 0
|
||||
TXD1 = 0b010 // Mini UART - Alternate function 5
|
||||
]
|
||||
],
|
||||
|
||||
/// GPIO Pull-up/down Clock Register 0
|
||||
GPPUDCLK0 [
|
||||
/// Pin 15
|
||||
PUDCLK15 OFFSET(15) NUMBITS(1) [
|
||||
NoEffect = 0,
|
||||
AssertClock = 1
|
||||
],
|
||||
|
||||
/// Pin 14
|
||||
PUDCLK14 OFFSET(14) NUMBITS(1) [
|
||||
NoEffect = 0,
|
||||
AssertClock = 1
|
||||
]
|
||||
]
|
||||
}
|
||||
|
||||
#[allow(non_snake_case)]
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
pub GPFSEL0: ReadWrite<u32>, // 0x00
|
||||
pub GPFSEL1: ReadWrite<u32, GPFSEL1::Register>, // 0x04
|
||||
pub GPFSEL2: ReadWrite<u32>, // 0x08
|
||||
pub GPFSEL3: ReadWrite<u32>, // 0x0C
|
||||
pub GPFSEL4: ReadWrite<u32>, // 0x10
|
||||
pub GPFSEL5: ReadWrite<u32>, // 0x14
|
||||
__reserved_0: u32, // 0x18
|
||||
GPSET0: ReadWrite<u32>, // 0x1C
|
||||
GPSET1: ReadWrite<u32>, // 0x20
|
||||
__reserved_1: u32, //
|
||||
GPCLR0: ReadWrite<u32>, // 0x28
|
||||
__reserved_2: [u32; 2], //
|
||||
GPLEV0: ReadWrite<u32>, // 0x34
|
||||
GPLEV1: ReadWrite<u32>, // 0x38
|
||||
__reserved_3: u32, //
|
||||
GPEDS0: ReadWrite<u32>, // 0x40
|
||||
GPEDS1: ReadWrite<u32>, // 0x44
|
||||
__reserved_4: [u32; 7], //
|
||||
GPHEN0: ReadWrite<u32>, // 0x64
|
||||
GPHEN1: ReadWrite<u32>, // 0x68
|
||||
__reserved_5: [u32; 10], //
|
||||
pub GPPUD: ReadWrite<u32>, // 0x94
|
||||
pub GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>, // 0x98
|
||||
pub GPPUDCLK1: ReadWrite<u32>, // 0x9C
|
||||
}
|
||||
|
||||
/// The driver's private data.
|
||||
struct GPIOInner {
|
||||
base_addr: usize,
|
||||
}
|
||||
|
||||
/// Deref to RegisterBlock.
|
||||
impl ops::Deref for GPIOInner {
|
||||
type Target = RegisterBlock;
|
||||
|
||||
fn deref(&self) -> &Self::Target {
|
||||
unsafe { &*self.ptr() }
|
||||
}
|
||||
}
|
||||
|
||||
impl GPIOInner {
|
||||
const fn new(base_addr: usize) -> GPIOInner {
|
||||
GPIOInner { base_addr }
|
||||
}
|
||||
|
||||
/// Return a pointer to the register block.
|
||||
fn ptr(&self) -> *const RegisterBlock {
|
||||
self.base_addr as *const _
|
||||
}
|
||||
|
||||
/// Map Mini UART as standard output.
|
||||
///
|
||||
/// TX to pin 14
|
||||
/// RX to pin 15
|
||||
fn map_mini_uart(&mut self) {
|
||||
// Map to pins.
|
||||
self.GPFSEL1
|
||||
.modify(GPFSEL1::FSEL14::TXD1 + GPFSEL1::FSEL15::RXD1);
|
||||
|
||||
// Enable pins 14 and 15.
|
||||
self.GPPUD.set(0);
|
||||
for _ in 0..150 {
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
self.GPPUDCLK0
|
||||
.write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
|
||||
for _ in 0..150 {
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
self.GPPUDCLK0.set(0);
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// OS interface implementations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/// The driver's public data.
|
||||
pub struct GPIO {
|
||||
inner: NullLock<GPIOInner>,
|
||||
}
|
||||
|
||||
impl GPIO {
|
||||
pub const unsafe fn new(base_addr: usize) -> GPIO {
|
||||
GPIO {
|
||||
inner: NullLock::new(GPIOInner::new(base_addr)),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl interface::driver::DeviceDriver for GPIO {
|
||||
fn compatible(&self) -> &str {
|
||||
"GPIO"
|
||||
}
|
||||
|
||||
fn init(&self) -> interface::driver::Result {
|
||||
use interface::sync::Mutex;
|
||||
|
||||
let mut r = &self.inner;
|
||||
r.lock(|i| i.map_mini_uart());
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,263 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! Mini UART driver.
|
||||
|
||||
use super::super::NullLock;
|
||||
use crate::interface;
|
||||
use core::{fmt, ops};
|
||||
use cortex_a::asm;
|
||||
use register::{mmio::*, register_bitfields};
|
||||
|
||||
// Mini UART registers.
|
||||
//
|
||||
// Descriptions taken from
|
||||
// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
|
||||
register_bitfields! {
|
||||
u32,
|
||||
|
||||
/// Auxiliary enables
|
||||
AUX_ENABLES [
|
||||
/// If set the mini UART is enabled. The UART will immediately
|
||||
/// start receiving data, especially if the UART1_RX line is
|
||||
/// low.
|
||||
/// If clear the mini UART is disabled. That also disables any
|
||||
/// mini UART register access
|
||||
MINI_UART_ENABLE OFFSET(0) NUMBITS(1) []
|
||||
],
|
||||
|
||||
/// Mini Uart Interrupt Identify
|
||||
AUX_MU_IIR [
|
||||
/// Writing with bit 1 set will clear the receive FIFO
|
||||
/// Writing with bit 2 set will clear the transmit FIFO
|
||||
FIFO_CLEAR OFFSET(1) NUMBITS(2) [
|
||||
Rx = 0b01,
|
||||
Tx = 0b10,
|
||||
All = 0b11
|
||||
]
|
||||
],
|
||||
|
||||
/// Mini Uart Line Control
|
||||
AUX_MU_LCR [
|
||||
/// Mode the UART works in
|
||||
DATA_SIZE OFFSET(0) NUMBITS(2) [
|
||||
SevenBit = 0b00,
|
||||
EightBit = 0b11
|
||||
]
|
||||
],
|
||||
|
||||
/// Mini Uart Line Status
|
||||
AUX_MU_LSR [
|
||||
/// This bit is set if the transmit FIFO is empty and the transmitter is
|
||||
/// idle. (Finished shifting out the last bit).
|
||||
TX_IDLE OFFSET(6) NUMBITS(1) [],
|
||||
|
||||
/// This bit is set if the transmit FIFO can accept at least
|
||||
/// one byte.
|
||||
TX_EMPTY OFFSET(5) NUMBITS(1) [],
|
||||
|
||||
/// This bit is set if the receive FIFO holds at least 1
|
||||
/// symbol.
|
||||
DATA_READY OFFSET(0) NUMBITS(1) []
|
||||
],
|
||||
|
||||
/// Mini Uart Extra Control
|
||||
AUX_MU_CNTL [
|
||||
/// If this bit is set the mini UART transmitter is enabled.
|
||||
/// If this bit is clear the mini UART transmitter is disabled.
|
||||
TX_EN OFFSET(1) NUMBITS(1) [
|
||||
Disabled = 0,
|
||||
Enabled = 1
|
||||
],
|
||||
|
||||
/// If this bit is set the mini UART receiver is enabled.
|
||||
/// If this bit is clear the mini UART receiver is disabled.
|
||||
RX_EN OFFSET(0) NUMBITS(1) [
|
||||
Disabled = 0,
|
||||
Enabled = 1
|
||||
]
|
||||
],
|
||||
|
||||
/// Mini Uart Baudrate
|
||||
AUX_MU_BAUD [
|
||||
/// Mini UART baudrate counter
|
||||
RATE OFFSET(0) NUMBITS(16) []
|
||||
]
|
||||
}
|
||||
|
||||
#[allow(non_snake_case)]
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
__reserved_0: u32, // 0x00
|
||||
AUX_ENABLES: ReadWrite<u32, AUX_ENABLES::Register>, // 0x04
|
||||
__reserved_1: [u32; 14], // 0x08
|
||||
AUX_MU_IO: ReadWrite<u32>, // 0x40 - Mini Uart I/O Data
|
||||
AUX_MU_IER: WriteOnly<u32>, // 0x44 - Mini Uart Interrupt Enable
|
||||
AUX_MU_IIR: WriteOnly<u32, AUX_MU_IIR::Register>, // 0x48
|
||||
AUX_MU_LCR: WriteOnly<u32, AUX_MU_LCR::Register>, // 0x4C
|
||||
AUX_MU_MCR: WriteOnly<u32>, // 0x50
|
||||
AUX_MU_LSR: ReadOnly<u32, AUX_MU_LSR::Register>, // 0x54
|
||||
__reserved_2: [u32; 2], // 0x58
|
||||
AUX_MU_CNTL: WriteOnly<u32, AUX_MU_CNTL::Register>, // 0x60
|
||||
__reserved_3: u32, // 0x64
|
||||
AUX_MU_BAUD: WriteOnly<u32, AUX_MU_BAUD::Register>, // 0x68
|
||||
}
|
||||
|
||||
/// The driver's mutex protected part.
|
||||
struct MiniUartInner {
|
||||
base_addr: usize,
|
||||
chars_written: usize,
|
||||
}
|
||||
|
||||
/// Deref to RegisterBlock.
|
||||
///
|
||||
/// Allows writing
|
||||
/// ```
|
||||
/// self.MU_IER.read()
|
||||
/// ```
|
||||
/// instead of something along the lines of
|
||||
/// ```
|
||||
/// unsafe { (*MiniUart::ptr()).MU_IER.read() }
|
||||
/// ```
|
||||
impl ops::Deref for MiniUartInner {
|
||||
type Target = RegisterBlock;
|
||||
|
||||
fn deref(&self) -> &Self::Target {
|
||||
unsafe { &*self.ptr() }
|
||||
}
|
||||
}
|
||||
|
||||
impl MiniUartInner {
|
||||
const fn new(base_addr: usize) -> MiniUartInner {
|
||||
MiniUartInner {
|
||||
base_addr,
|
||||
chars_written: 0,
|
||||
}
|
||||
}
|
||||
|
||||
/// Return a pointer to the register block.
|
||||
fn ptr(&self) -> *const RegisterBlock {
|
||||
self.base_addr as *const _
|
||||
}
|
||||
|
||||
/// Set up baud rate and characteristics (115200 8N1).
|
||||
fn init(&mut self) -> interface::driver::Result {
|
||||
self.AUX_ENABLES.modify(AUX_ENABLES::MINI_UART_ENABLE::SET);
|
||||
self.AUX_MU_IER.set(0);
|
||||
self.AUX_MU_CNTL.set(0);
|
||||
self.AUX_MU_LCR.write(AUX_MU_LCR::DATA_SIZE::EightBit);
|
||||
self.AUX_MU_MCR.set(0);
|
||||
self.AUX_MU_IER.set(0);
|
||||
self.AUX_MU_IIR.write(AUX_MU_IIR::FIFO_CLEAR::All);
|
||||
self.AUX_MU_BAUD.write(AUX_MU_BAUD::RATE.val(270)); // 115200 baud
|
||||
|
||||
// Enable receive and send.
|
||||
self.AUX_MU_CNTL
|
||||
.write(AUX_MU_CNTL::RX_EN::Enabled + AUX_MU_CNTL::TX_EN::Enabled);
|
||||
|
||||
// Clear FIFOs before using the device.
|
||||
self.AUX_MU_IIR.write(AUX_MU_IIR::FIFO_CLEAR::All);
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Send a character.
|
||||
fn write_char(&mut self, c: char) {
|
||||
// Wait until we can send.
|
||||
loop {
|
||||
if self.AUX_MU_LSR.is_set(AUX_MU_LSR::TX_EMPTY) {
|
||||
break;
|
||||
}
|
||||
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
// Write the character to the buffer.
|
||||
self.AUX_MU_IO.set(c as u32);
|
||||
}
|
||||
}
|
||||
|
||||
/// Implementing `core::fmt::Write` enables usage of the `format_args!` macros,
|
||||
/// which in turn are used to implement the `kernel`'s `print!` and `println!`
|
||||
/// macros. By implementing `write_str()`, we get `write_fmt()` automatically.
|
||||
///
|
||||
/// The function takes an `&mut self`, so it must be implemented for the inner
|
||||
/// struct.
|
||||
///
|
||||
/// See [`src/print.rs`].
|
||||
///
|
||||
/// [`src/print.rs`]: ../../print/index.html
|
||||
impl fmt::Write for MiniUartInner {
|
||||
fn write_str(&mut self, s: &str) -> fmt::Result {
|
||||
for c in s.chars() {
|
||||
// Convert newline to carrige return + newline.
|
||||
if c == '\n' {
|
||||
self.write_char('\r')
|
||||
}
|
||||
|
||||
self.write_char(c);
|
||||
}
|
||||
|
||||
self.chars_written += s.len();
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// OS interface implementations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/// The driver's main struct.
|
||||
pub struct MiniUart {
|
||||
inner: NullLock<MiniUartInner>,
|
||||
}
|
||||
|
||||
impl MiniUart {
|
||||
/// # Safety
|
||||
///
|
||||
/// The user must ensure to provide the correct `base_addr`.
|
||||
pub const unsafe fn new(base_addr: usize) -> MiniUart {
|
||||
MiniUart {
|
||||
inner: NullLock::new(MiniUartInner::new(base_addr)),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl interface::driver::DeviceDriver for MiniUart {
|
||||
fn compatible(&self) -> &str {
|
||||
"MiniUart"
|
||||
}
|
||||
|
||||
fn init(&self) -> interface::driver::Result {
|
||||
use interface::sync::Mutex;
|
||||
|
||||
let mut r = &self.inner;
|
||||
r.lock(|i| i.init())
|
||||
}
|
||||
}
|
||||
|
||||
/// Passthrough of `args` to the `core::fmt::Write` implementation, but guarded
|
||||
/// by a Mutex to serialize access.
|
||||
impl interface::console::Write for MiniUart {
|
||||
fn write_fmt(&self, args: core::fmt::Arguments) -> fmt::Result {
|
||||
use interface::sync::Mutex;
|
||||
|
||||
// Fully qualified syntax for the call to
|
||||
// `core::fmt::Write::write:fmt()` to increase readability.
|
||||
let mut r = &self.inner;
|
||||
r.lock(|i| fmt::Write::write_fmt(i, args))
|
||||
}
|
||||
}
|
||||
|
||||
impl interface::console::Read for MiniUart {}
|
||||
|
||||
impl interface::console::Statistics for MiniUart {
|
||||
fn chars_written(&self) -> usize {
|
||||
use interface::sync::Mutex;
|
||||
|
||||
let mut r = &self.inner;
|
||||
r.lock(|i| i.chars_written)
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,35 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
*/
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Set current address to the value from which the RPi3 starts execution */
|
||||
. = 0x80000;
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text._start) *(.text*)
|
||||
}
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata*)
|
||||
}
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data*)
|
||||
}
|
||||
|
||||
/* Align to 8 byte boundary */
|
||||
.bss ALIGN(8):
|
||||
{
|
||||
__bss_start = .;
|
||||
*(.bss*);
|
||||
__bss_end = .;
|
||||
}
|
||||
|
||||
/DISCARD/ : { *(.comment*) }
|
||||
}
|
||||
@ -0,0 +1,13 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! The board's memory map.
|
||||
|
||||
/// Physical devices.
|
||||
#[rustfmt::skip]
|
||||
pub mod mmio {
|
||||
pub const BASE: usize = 0x3F00_0000;
|
||||
pub const GPIO_BASE: usize = BASE + 0x0020_0000;
|
||||
pub const MINI_UART_BASE: usize = BASE + 0x0021_5000;
|
||||
}
|
||||
@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! A panic handler that infinitely waits.
|
||||
|
||||
use crate::println;
|
||||
use core::panic::PanicInfo;
|
||||
|
||||
#[panic_handler]
|
||||
fn panic(info: &PanicInfo) -> ! {
|
||||
if let Some(args) = info.message() {
|
||||
println!("Kernel panic: {}", args);
|
||||
} else {
|
||||
println!("Kernel panic!");
|
||||
}
|
||||
|
||||
super::wait_forever()
|
||||
}
|
||||
@ -0,0 +1,47 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! Board-specific synchronization primitives.
|
||||
|
||||
use crate::interface;
|
||||
use core::cell::UnsafeCell;
|
||||
|
||||
/// A pseudo-lock for teaching purposes.
|
||||
///
|
||||
/// Used to introduce [interior mutability].
|
||||
///
|
||||
/// In contrast to a real Mutex implementation, does not protect against
|
||||
/// concurrent access to the contained data. This part is preserved for later
|
||||
/// lessons.
|
||||
///
|
||||
/// The lock will only be used as long as it is safe to do so, i.e. as long as
|
||||
/// the kernel is executing single-threaded, aka only running on a single core
|
||||
/// with interrupts disabled.
|
||||
///
|
||||
/// [interior mutability]: https://doc.rust-lang.org/std/cell/index.html
|
||||
pub struct NullLock<T: ?Sized> {
|
||||
data: UnsafeCell<T>,
|
||||
}
|
||||
|
||||
unsafe impl<T: ?Sized + Send> Send for NullLock<T> {}
|
||||
unsafe impl<T: ?Sized + Send> Sync for NullLock<T> {}
|
||||
|
||||
impl<T> NullLock<T> {
|
||||
pub const fn new(data: T) -> NullLock<T> {
|
||||
NullLock {
|
||||
data: UnsafeCell::new(data),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<T> interface::sync::Mutex for &NullLock<T> {
|
||||
type Data = T;
|
||||
|
||||
fn lock<R>(&mut self, f: impl FnOnce(&mut Self::Data) -> R) -> R {
|
||||
// In a real lock, there would be code encapsulating this line that
|
||||
// ensures that this mutable reference will ever only be given out once
|
||||
// at a time.
|
||||
f(unsafe { &mut *self.data.get() })
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,104 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! Trait definitions for coupling `kernel` and `BSP` code.
|
||||
//!
|
||||
//! ```
|
||||
//! +-------------------+
|
||||
//! | Interface (Trait) |
|
||||
//! | |
|
||||
//! +--+-------------+--+
|
||||
//! ^ ^
|
||||
//! | |
|
||||
//! | |
|
||||
//! +----------+--+ +--+----------+
|
||||
//! | Kernel code | | BSP Code |
|
||||
//! | | | |
|
||||
//! +-------------+ +-------------+
|
||||
//! ```
|
||||
|
||||
/// System console operations.
|
||||
pub mod console {
|
||||
use core::fmt;
|
||||
|
||||
/// Console write functions.
|
||||
pub trait Write {
|
||||
fn write_fmt(&self, args: fmt::Arguments) -> fmt::Result;
|
||||
}
|
||||
|
||||
/// Console read functions.
|
||||
pub trait Read {
|
||||
fn read_char(&self) -> char {
|
||||
' '
|
||||
}
|
||||
}
|
||||
|
||||
/// Console statistics.
|
||||
pub trait Statistics {
|
||||
/// Return the number of characters written.
|
||||
fn chars_written(&self) -> usize {
|
||||
0
|
||||
}
|
||||
|
||||
/// Return the number of characters read.
|
||||
fn chars_read(&self) -> usize {
|
||||
0
|
||||
}
|
||||
}
|
||||
|
||||
/// Trait alias for a full-fledged console.
|
||||
pub trait All = Write + Read + Statistics;
|
||||
}
|
||||
|
||||
/// Synchronization primitives.
|
||||
pub mod sync {
|
||||
/// Any object implementing this trait guarantees exclusive access to the
|
||||
/// data contained within the mutex for the duration of the lock.
|
||||
///
|
||||
/// The trait follows the [Rust embedded WG's
|
||||
/// proposal](https://github.com/korken89/wg/blob/master/rfcs/0377-mutex-trait.md)
|
||||
/// and therefore provides some goodness such as [deadlock
|
||||
/// prevention](https://github.com/korken89/wg/blob/master/rfcs/0377-mutex-trait.md#design-decisions-and-compatibility).
|
||||
///
|
||||
/// # Example
|
||||
///
|
||||
/// Since the lock function takes an `&mut self` to enable
|
||||
/// deadlock-prevention, the trait is best implemented **for a reference to
|
||||
/// a container struct**, and has a usage pattern that might feel strange at
|
||||
/// first:
|
||||
///
|
||||
/// ```
|
||||
/// static MUT: Mutex<RefCell<i32>> = Mutex::new(RefCell::new(0));
|
||||
///
|
||||
/// fn foo() {
|
||||
/// let mut r = &MUT; // Note that r is mutable
|
||||
/// r.lock(|data| *data += 1);
|
||||
/// }
|
||||
/// ```
|
||||
pub trait Mutex {
|
||||
/// Type of data encapsulated by the mutex.
|
||||
type Data;
|
||||
|
||||
/// Creates a critical section and grants temporary mutable access to
|
||||
/// the encapsulated data.
|
||||
fn lock<R>(&mut self, f: impl FnOnce(&mut Self::Data) -> R) -> R;
|
||||
}
|
||||
}
|
||||
|
||||
/// Driver interfaces.
|
||||
pub mod driver {
|
||||
/// Driver result type, e.g. for indicating successful driver init.
|
||||
pub type Result = core::result::Result<(), ()>;
|
||||
|
||||
/// Device Driver operations.
|
||||
pub trait DeviceDriver {
|
||||
/// Return a compatibility string for identifying the driver.
|
||||
fn compatible(&self) -> &str;
|
||||
|
||||
/// Called by the kernel to bring up the device.
|
||||
fn init(&self) -> Result {
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,60 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
// Rust embedded logo for `make doc`.
|
||||
#![doc(html_logo_url = "https://git.io/JeGIp")]
|
||||
|
||||
//! The `kernel`
|
||||
//!
|
||||
//! The `kernel` is composed by glueing together hardware-specific Board Support
|
||||
//! Package (`BSP`) code and hardware-agnostic `kernel` code through the
|
||||
//! [`kernel::interface`] traits.
|
||||
//!
|
||||
//! [`kernel::interface`]: interface/index.html
|
||||
|
||||
#![feature(format_args_nl)]
|
||||
#![feature(panic_info_message)]
|
||||
#![feature(trait_alias)]
|
||||
#![no_main]
|
||||
#![no_std]
|
||||
|
||||
// This module conditionally includes the correct `BSP` which provides the
|
||||
// `_start()` function, the first function to run.
|
||||
mod bsp;
|
||||
|
||||
// Afterwards, `BSP`'s early init code calls `runtime_init::init()` of this
|
||||
// module, which on completion, jumps to `kernel_entry()`.
|
||||
mod runtime_init;
|
||||
|
||||
mod interface;
|
||||
mod print;
|
||||
|
||||
/// Entrypoint of the `kernel`.
|
||||
fn kernel_entry() -> ! {
|
||||
use interface::console::Statistics;
|
||||
|
||||
// Initialize the BSP's device drivers.
|
||||
for i in bsp::device_drivers().iter() {
|
||||
if let Err(()) = i.init() {
|
||||
// This message will only be readable if, at the time of failure,
|
||||
// the return value of `bsp::console()` is already in functioning
|
||||
// state.
|
||||
panic!("Error loading driver: {}", i.compatible())
|
||||
}
|
||||
}
|
||||
|
||||
// If all drivers are loaded, UART is functional now and `println!()` calls
|
||||
// are transmitted on the physical wires.
|
||||
println!("[0] Hello from pure Rust!");
|
||||
|
||||
println!("[1] Drivers probed:");
|
||||
for (i, driver) in bsp::device_drivers().iter().enumerate() {
|
||||
println!(" {}. {}", i + 1, driver.compatible());
|
||||
}
|
||||
|
||||
println!("[2] Chars written: {}", bsp::console().chars_written());
|
||||
|
||||
println!("[3] Stopping here.");
|
||||
bsp::wait_forever()
|
||||
}
|
||||
@ -0,0 +1,34 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! Printing facilities.
|
||||
|
||||
use crate::bsp;
|
||||
use crate::interface;
|
||||
use core::fmt;
|
||||
|
||||
/// Prints without a newline.
|
||||
///
|
||||
/// Carbon copy from https://doc.rust-lang.org/src/std/macros.rs.html
|
||||
#[macro_export]
|
||||
macro_rules! print {
|
||||
($($arg:tt)*) => ($crate::print::_print(format_args!($($arg)*)));
|
||||
}
|
||||
|
||||
/// Prints with a newline.
|
||||
///
|
||||
/// Carbon copy from https://doc.rust-lang.org/src/std/macros.rs.html
|
||||
#[macro_export]
|
||||
macro_rules! println {
|
||||
() => ($crate::print!("\n"));
|
||||
($($arg:tt)*) => ({
|
||||
$crate::print::_print(format_args_nl!($($arg)*));
|
||||
})
|
||||
}
|
||||
|
||||
pub fn _print(args: fmt::Arguments) {
|
||||
use interface::console::Write;
|
||||
|
||||
bsp::console().write_fmt(args).unwrap();
|
||||
}
|
||||
@ -0,0 +1,27 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! Rust runtime initialization code.
|
||||
|
||||
/// Equivalent to `crt0` or `c0` code in C/C++ world. Clears the `bss` section,
|
||||
/// then calls the kernel entry.
|
||||
///
|
||||
/// Called from `BSP` code.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// - Only a single core must be active and running this function.
|
||||
#[no_mangle]
|
||||
pub unsafe fn init() -> ! {
|
||||
extern "C" {
|
||||
// Boundaries of the .bss section, provided by the linker script
|
||||
static mut __bss_start: u64;
|
||||
static mut __bss_end: u64;
|
||||
}
|
||||
|
||||
// Zero out the .bss section
|
||||
r0::zero_bss(&mut __bss_start, &mut __bss_end);
|
||||
|
||||
crate::kernel_entry()
|
||||
}
|
||||
Loading…
Reference in New Issue