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UART: Fix FBRD

Browse Source 
Closes #70

Co-authored-by: Carl Fredrik Samson <cfsamson@users.noreply.github.com>
pull/71/head
Andre Richter 4 years ago
parent 519be514a5
commit 87e74f62cd
No known key found for this signature in database
GPG Key ID: 2116C1AB102F615E
11 changed files with 11 additions and 11 deletions
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2
06_drivers_gpio_uart/README.md
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@ -460,7 +460,7 @@ diff -uNr 05_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 06_dri
+
+ self.registers.ICR.write(ICR::ALL::CLEAR);
+ self.registers.IBRD.write(IBRD::IBRD.val(13));
+ self.registers.FBRD.write(FBRD::FBRD.val(2));
+ self.registers.FBRD.write(FBRD::FBRD.val(1));
+ self.registers
+ .LCRH
+ .write(LCRH::WLEN::EightBit + LCRH::FEN::FifosEnabled); // 8N1 + Fifo on

2
06_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -182,7 +182,7 @@ impl PL011UartInner {
self.registers.ICR.write(ICR::ALL::CLEAR);
self.registers.IBRD.write(IBRD::IBRD.val(13));
self.registers.FBRD.write(FBRD::FBRD.val(2));
self.registers.FBRD.write(FBRD::FBRD.val(1));
self.registers
.LCRH
.write(LCRH::WLEN::EightBit + LCRH::FEN::FifosEnabled); // 8N1 + Fifo on

2
07_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -182,7 +182,7 @@ impl PL011UartInner {
self.registers.ICR.write(ICR::ALL::CLEAR);
self.registers.IBRD.write(IBRD::IBRD.val(13));
self.registers.FBRD.write(FBRD::FBRD.val(2));
self.registers.FBRD.write(FBRD::FBRD.val(1));
self.registers
.LCRH
.write(LCRH::WLEN::EightBit + LCRH::FEN::FifosEnabled); // 8N1 + Fifo on

2
08_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -182,7 +182,7 @@ impl PL011UartInner {
self.registers.ICR.write(ICR::ALL::CLEAR);
self.registers.IBRD.write(IBRD::IBRD.val(13));
self.registers.FBRD.write(FBRD::FBRD.val(2));
self.registers.FBRD.write(FBRD::FBRD.val(1));
self.registers
.LCRH
.write(LCRH::WLEN::EightBit + LCRH::FEN::FifosEnabled); // 8N1 + Fifo on

2
09_hw_debug_JTAG/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -182,7 +182,7 @@ impl PL011UartInner {
self.registers.ICR.write(ICR::ALL::CLEAR);
self.registers.IBRD.write(IBRD::IBRD.val(13));
self.registers.FBRD.write(FBRD::FBRD.val(2));
self.registers.FBRD.write(FBRD::FBRD.val(1));
self.registers
.LCRH
.write(LCRH::WLEN::EightBit + LCRH::FEN::FifosEnabled); // 8N1 + Fifo on

2
10_privilege_level/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -182,7 +182,7 @@ impl PL011UartInner {
self.registers.ICR.write(ICR::ALL::CLEAR);
self.registers.IBRD.write(IBRD::IBRD.val(13));
self.registers.FBRD.write(FBRD::FBRD.val(2));
self.registers.FBRD.write(FBRD::FBRD.val(1));
self.registers
.LCRH
.write(LCRH::WLEN::EightBit + LCRH::FEN::FifosEnabled); // 8N1 + Fifo on

2
11_virtual_memory/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -182,7 +182,7 @@ impl PL011UartInner {
self.registers.ICR.write(ICR::ALL::CLEAR);
self.registers.IBRD.write(IBRD::IBRD.val(13));
self.registers.FBRD.write(FBRD::FBRD.val(2));
self.registers.FBRD.write(FBRD::FBRD.val(1));
self.registers
.LCRH
.write(LCRH::WLEN::EightBit + LCRH::FEN::FifosEnabled); // 8N1 + Fifo on

2
12_exceptions_part1_groundwork/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -182,7 +182,7 @@ impl PL011UartInner {
self.registers.ICR.write(ICR::ALL::CLEAR);
self.registers.IBRD.write(IBRD::IBRD.val(13));
self.registers.FBRD.write(FBRD::FBRD.val(2));
self.registers.FBRD.write(FBRD::FBRD.val(1));
self.registers
.LCRH
.write(LCRH::WLEN::EightBit + LCRH::FEN::FifosEnabled); // 8N1 + Fifo on

2
13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -182,7 +182,7 @@ impl PL011UartInner {
self.registers.ICR.write(ICR::ALL::CLEAR);
self.registers.IBRD.write(IBRD::IBRD.val(13));
self.registers.FBRD.write(FBRD::FBRD.val(2));
self.registers.FBRD.write(FBRD::FBRD.val(1));
self.registers
.LCRH
.write(LCRH::WLEN::EightBit + LCRH::FEN::FifosEnabled); // 8N1 + Fifo on

2
14_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -234,7 +234,7 @@ impl PL011UartInner {
self.registers.ICR.write(ICR::ALL::CLEAR);
self.registers.IBRD.write(IBRD::IBRD.val(13));
self.registers.FBRD.write(FBRD::FBRD.val(2));
self.registers.FBRD.write(FBRD::FBRD.val(1));
self.registers
.LCRH
.write(LCRH::WLEN::EightBit + LCRH::FEN::FifosEnabled); // 8N1 + Fifo on

2
X1_JTAG_boot/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -182,7 +182,7 @@ impl PL011UartInner {
self.registers.ICR.write(ICR::ALL::CLEAR);
self.registers.IBRD.write(IBRD::IBRD.val(13));
self.registers.FBRD.write(FBRD::FBRD.val(2));
self.registers.FBRD.write(FBRD::FBRD.val(1));
self.registers
.LCRH
.write(LCRH::WLEN::EightBit + LCRH::FEN::FifosEnabled); // 8N1 + Fifo on

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