Be more consistent in boot.rs GPR choices

pull/171/head
Andre Richter 2 years ago
parent c21641e9b5
commit b22b0b1792
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GPG Key ID: 2116C1AB102F615E

@ -117,10 +117,10 @@ diff -uNr 01_wait_forever/src/_arch/aarch64/cpu/boot.s 02_runtime_init/src/_arch
//------------------------------------------------------------------------------
_start:
+ // Only proceed on the boot core. Park it otherwise.
+ mrs x1, MPIDR_EL1
+ and x1, x1, {CONST_CORE_ID_MASK}
+ ldr x2, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
+ cmp x1, x2
+ mrs x0, MPIDR_EL1
+ and x0, x0, {CONST_CORE_ID_MASK}
+ ldr x1, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
+ cmp x0, x1
+ b.ne .L_parking_loop
+
+ // If execution reaches here, it is the boot core.

@ -28,10 +28,10 @@
//------------------------------------------------------------------------------
_start:
// Only proceed on the boot core. Park it otherwise.
mrs x1, MPIDR_EL1
and x1, x1, {CONST_CORE_ID_MASK}
ldr x2, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x1, x2
mrs x0, MPIDR_EL1
and x0, x0, {CONST_CORE_ID_MASK}
ldr x1, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x0, x1
b.ne .L_parking_loop
// If execution reaches here, it is the boot core.

@ -28,10 +28,10 @@
//------------------------------------------------------------------------------
_start:
// Only proceed on the boot core. Park it otherwise.
mrs x1, MPIDR_EL1
and x1, x1, {CONST_CORE_ID_MASK}
ldr x2, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x1, x2
mrs x0, MPIDR_EL1
and x0, x0, {CONST_CORE_ID_MASK}
ldr x1, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x0, x1
b.ne .L_parking_loop
// If execution reaches here, it is the boot core.

@ -28,10 +28,10 @@
//------------------------------------------------------------------------------
_start:
// Only proceed on the boot core. Park it otherwise.
mrs x1, MPIDR_EL1
and x1, x1, {CONST_CORE_ID_MASK}
ldr x2, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x1, x2
mrs x0, MPIDR_EL1
and x0, x0, {CONST_CORE_ID_MASK}
ldr x1, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x0, x1
b.ne .L_parking_loop
// If execution reaches here, it is the boot core.

@ -28,10 +28,10 @@
//------------------------------------------------------------------------------
_start:
// Only proceed on the boot core. Park it otherwise.
mrs x1, MPIDR_EL1
and x1, x1, {CONST_CORE_ID_MASK}
ldr x2, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x1, x2
mrs x0, MPIDR_EL1
and x0, x0, {CONST_CORE_ID_MASK}
ldr x1, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x0, x1
b.ne .L_parking_loop
// If execution reaches here, it is the boot core.

@ -39,10 +39,10 @@
//------------------------------------------------------------------------------
_start:
// Only proceed on the boot core. Park it otherwise.
mrs x1, MPIDR_EL1
and x1, x1, {CONST_CORE_ID_MASK}
ldr x2, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x1, x2
mrs x0, MPIDR_EL1
and x0, x0, {CONST_CORE_ID_MASK}
ldr x1, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x0, x1
b.ne .L_parking_loop
// If execution reaches here, it is the boot core.

@ -28,10 +28,10 @@
//------------------------------------------------------------------------------
_start:
// Only proceed on the boot core. Park it otherwise.
mrs x1, MPIDR_EL1
and x1, x1, {CONST_CORE_ID_MASK}
ldr x2, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x1, x2
mrs x0, MPIDR_EL1
and x0, x0, {CONST_CORE_ID_MASK}
ldr x1, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x0, x1
b.ne .L_parking_loop
// If execution reaches here, it is the boot core.

@ -28,10 +28,10 @@
//------------------------------------------------------------------------------
_start:
// Only proceed on the boot core. Park it otherwise.
mrs x1, MPIDR_EL1
and x1, x1, {CONST_CORE_ID_MASK}
ldr x2, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x1, x2
mrs x0, MPIDR_EL1
and x0, x0, {CONST_CORE_ID_MASK}
ldr x1, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x0, x1
b.ne .L_parking_loop
// If execution reaches here, it is the boot core.

@ -291,7 +291,7 @@ diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/cpu/boot.rs 09_privilege_level/src/
diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/cpu/boot.s 09_privilege_level/src/_arch/aarch64/cpu/boot.s
--- 08_hw_debug_JTAG/src/_arch/aarch64/cpu/boot.s
+++ 09_privilege_level/src/_arch/aarch64/cpu/boot.s
@@ -27,6 +27,11 @@
@@ -27,11 +27,16 @@
// fn _start()
//------------------------------------------------------------------------------
_start:
@ -301,8 +301,17 @@ diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/cpu/boot.s 09_privilege_level/src/_
+ b.ne .L_parking_loop
+
// Only proceed on the boot core. Park it otherwise.
mrs x1, MPIDR_EL1
and x1, x1, {CONST_CORE_ID_MASK}
- mrs x0, MPIDR_EL1
- and x0, x0, {CONST_CORE_ID_MASK}
- ldr x1, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
- cmp x0, x1
+ mrs x1, MPIDR_EL1
+ and x1, x1, {CONST_CORE_ID_MASK}
+ ldr x2, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
+ cmp x1, x2
b.ne .L_parking_loop
// If execution reaches here, it is the boot core.
@@ -48,7 +53,7 @@
// Prepare the jump to Rust code.

@ -432,20 +432,20 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/kernel/src/_arch/aarch64/cpu/b
+ // Setting the stack pointer to this value ensures that anything that still runs in EL2,
+ // until the kernel returns to EL1 with the MMU enabled, works as well. After the return to
+ // EL1, the virtual address of the stack retrieved above will be used.
+ ADR_REL x4, __boot_core_stack_end_exclusive
+ mov sp, x4
+ ADR_REL x3, __boot_core_stack_end_exclusive
+ mov sp, x3
// Read the CPU's timer counter frequency and store it in ARCH_TIMER_COUNTER_FREQUENCY.
// Abort if the frequency read back as 0.
- ADR_REL x2, ARCH_TIMER_COUNTER_FREQUENCY // provided by aarch64/time.rs
- mrs x3, CNTFRQ_EL0
- cmp x3, xzr
+ ADR_REL x5, ARCH_TIMER_COUNTER_FREQUENCY // provided by aarch64/time.rs
+ mrs x6, CNTFRQ_EL0
+ cmp x6, xzr
+ ADR_REL x4, ARCH_TIMER_COUNTER_FREQUENCY // provided by aarch64/time.rs
+ mrs x5, CNTFRQ_EL0
+ cmp x5, xzr
b.eq .L_parking_loop
- str w3, [x2]
+ str w6, [x5]
+ str w5, [x4]
- // Jump to Rust code. x0 and x1 hold the function arguments provided to _start_rust().
+ // Jump to Rust code. x0, x1 and x2 hold the function arguments provided to _start_rust().

@ -81,16 +81,16 @@ _start:
// Setting the stack pointer to this value ensures that anything that still runs in EL2,
// until the kernel returns to EL1 with the MMU enabled, works as well. After the return to
// EL1, the virtual address of the stack retrieved above will be used.
ADR_REL x4, __boot_core_stack_end_exclusive
mov sp, x4
ADR_REL x3, __boot_core_stack_end_exclusive
mov sp, x3
// Read the CPU's timer counter frequency and store it in ARCH_TIMER_COUNTER_FREQUENCY.
// Abort if the frequency read back as 0.
ADR_REL x5, ARCH_TIMER_COUNTER_FREQUENCY // provided by aarch64/time.rs
mrs x6, CNTFRQ_EL0
cmp x6, xzr
ADR_REL x4, ARCH_TIMER_COUNTER_FREQUENCY // provided by aarch64/time.rs
mrs x5, CNTFRQ_EL0
cmp x5, xzr
b.eq .L_parking_loop
str w6, [x5]
str w5, [x4]
// Jump to Rust code. x0, x1 and x2 hold the function arguments provided to _start_rust().
b _start_rust

@ -81,16 +81,16 @@ _start:
// Setting the stack pointer to this value ensures that anything that still runs in EL2,
// until the kernel returns to EL1 with the MMU enabled, works as well. After the return to
// EL1, the virtual address of the stack retrieved above will be used.
ADR_REL x4, __boot_core_stack_end_exclusive
mov sp, x4
ADR_REL x3, __boot_core_stack_end_exclusive
mov sp, x3
// Read the CPU's timer counter frequency and store it in ARCH_TIMER_COUNTER_FREQUENCY.
// Abort if the frequency read back as 0.
ADR_REL x5, ARCH_TIMER_COUNTER_FREQUENCY // provided by aarch64/time.rs
mrs x6, CNTFRQ_EL0
cmp x6, xzr
ADR_REL x4, ARCH_TIMER_COUNTER_FREQUENCY // provided by aarch64/time.rs
mrs x5, CNTFRQ_EL0
cmp x5, xzr
b.eq .L_parking_loop
str w6, [x5]
str w5, [x4]
// Jump to Rust code. x0, x1 and x2 hold the function arguments provided to _start_rust().
b _start_rust

@ -81,16 +81,16 @@ _start:
// Setting the stack pointer to this value ensures that anything that still runs in EL2,
// until the kernel returns to EL1 with the MMU enabled, works as well. After the return to
// EL1, the virtual address of the stack retrieved above will be used.
ADR_REL x4, __boot_core_stack_end_exclusive
mov sp, x4
ADR_REL x3, __boot_core_stack_end_exclusive
mov sp, x3
// Read the CPU's timer counter frequency and store it in ARCH_TIMER_COUNTER_FREQUENCY.
// Abort if the frequency read back as 0.
ADR_REL x5, ARCH_TIMER_COUNTER_FREQUENCY // provided by aarch64/time.rs
mrs x6, CNTFRQ_EL0
cmp x6, xzr
ADR_REL x4, ARCH_TIMER_COUNTER_FREQUENCY // provided by aarch64/time.rs
mrs x5, CNTFRQ_EL0
cmp x5, xzr
b.eq .L_parking_loop
str w6, [x5]
str w5, [x4]
// Jump to Rust code. x0, x1 and x2 hold the function arguments provided to _start_rust().
b _start_rust

@ -81,16 +81,16 @@ _start:
// Setting the stack pointer to this value ensures that anything that still runs in EL2,
// until the kernel returns to EL1 with the MMU enabled, works as well. After the return to
// EL1, the virtual address of the stack retrieved above will be used.
ADR_REL x4, __boot_core_stack_end_exclusive
mov sp, x4
ADR_REL x3, __boot_core_stack_end_exclusive
mov sp, x3
// Read the CPU's timer counter frequency and store it in ARCH_TIMER_COUNTER_FREQUENCY.
// Abort if the frequency read back as 0.
ADR_REL x5, ARCH_TIMER_COUNTER_FREQUENCY // provided by aarch64/time.rs
mrs x6, CNTFRQ_EL0
cmp x6, xzr
ADR_REL x4, ARCH_TIMER_COUNTER_FREQUENCY // provided by aarch64/time.rs
mrs x5, CNTFRQ_EL0
cmp x5, xzr
b.eq .L_parking_loop
str w6, [x5]
str w5, [x4]
// Jump to Rust code. x0, x1 and x2 hold the function arguments provided to _start_rust().
b _start_rust

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