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Shuffle constant to more fitting module

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pull/73/head
Andre Richter 4 years ago
parent bb83be8711
commit b585f64e30
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GPG Key ID: 2116C1AB102F615E
54 changed files with 311 additions and 263 deletions
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23
04_zero_overhead_abstraction/README.md
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@ -84,7 +84,7 @@ diff -uNr 03_hacky_hello_world/src/_arch/aarch64/cpu.rs 04_zero_overhead_abstrac
+
+ // Expect the boot core to start in EL2.
+ if bsp::cpu::BOOT_CORE_ID == cpu::smp::core_id() {
+ SP.set(bsp::cpu::BOOT_CORE_STACK_START);
+ SP.set(bsp::memory::BOOT_CORE_STACK_START as u64);
+ runtime_init::runtime_init()
+ } else {
+ // If not core0, infinitely wait for events.
@ -140,7 +140,7 @@ diff -uNr 03_hacky_hello_world/src/_arch/aarch64/cpu.S 04_zero_overhead_abstract
diff -uNr 03_hacky_hello_world/src/bsp/raspberrypi/cpu.rs 04_zero_overhead_abstraction/src/bsp/raspberrypi/cpu.rs
--- 03_hacky_hello_world/src/bsp/raspberrypi/cpu.rs
+++ 04_zero_overhead_abstraction/src/bsp/raspberrypi/cpu.rs
@@ -0,0 +1,15 @@
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0
+//
+// Copyright (c) 2018-2020 Andre Richter <andre.o.richter@gmail.com>
@ -153,18 +153,33 @@ diff -uNr 03_hacky_hello_world/src/bsp/raspberrypi/cpu.rs 04_zero_overhead_abstr
+
+/// Used by `arch` code to find the early boot core.
+pub const BOOT_CORE_ID: usize = 0;
diff -uNr 03_hacky_hello_world/src/bsp/raspberrypi/memory.rs 04_zero_overhead_abstraction/src/bsp/raspberrypi/memory.rs
--- 03_hacky_hello_world/src/bsp/raspberrypi/memory.rs
+++ 04_zero_overhead_abstraction/src/bsp/raspberrypi/memory.rs
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0
+//
+// Copyright (c) 2018-2020 Andre Richter <andre.o.richter@gmail.com>
+
+//! BSP Memory Management.
+
+//--------------------------------------------------------------------------------------------------
+// Public Definitions
+//--------------------------------------------------------------------------------------------------
+
+/// The early boot core's stack address.
+pub const BOOT_CORE_STACK_START: u64 = 0x80_000;
+pub const BOOT_CORE_STACK_START: usize = 0x80_000;
diff -uNr 03_hacky_hello_world/src/bsp/raspberrypi.rs 04_zero_overhead_abstraction/src/bsp/raspberrypi.rs
--- 03_hacky_hello_world/src/bsp/raspberrypi.rs
+++ 04_zero_overhead_abstraction/src/bsp/raspberrypi.rs
@@ -5,3 +5,4 @@
@@ -5,3 +5,5 @@
//! Top-level BSP file for the Raspberry Pi 3 and 4.
pub mod console;
+pub mod cpu;
+pub mod memory;
diff -uNr 03_hacky_hello_world/src/cpu/smp.rs 04_zero_overhead_abstraction/src/cpu/smp.rs
--- 03_hacky_hello_world/src/cpu/smp.rs

2
04_zero_overhead_abstraction/src/_arch/aarch64/cpu.rs
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@ -25,7 +25,7 @@ pub unsafe extern "C" fn _start() -> ! {
// Expect the boot core to start in EL2.
if bsp::cpu::BOOT_CORE_ID == cpu::smp::core_id() {
SP.set(bsp::cpu::BOOT_CORE_STACK_START);
SP.set(bsp::memory::BOOT_CORE_STACK_START as u64);
runtime_init::runtime_init()
} else {
// If not core0, infinitely wait for events.

1
04_zero_overhead_abstraction/src/bsp/raspberrypi.rs
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@ -6,3 +6,4 @@
pub mod console;
pub mod cpu;
pub mod memory;

3
04_zero_overhead_abstraction/src/bsp/raspberrypi/cpu.rs
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@ -10,6 +10,3 @@
/// Used by `arch` code to find the early boot core.
pub const BOOT_CORE_ID: usize = 0;
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: u64 = 0x80_000;

12
04_zero_overhead_abstraction/src/bsp/raspberrypi/memory.rs
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@ -0,0 +1,12 @@
// SPDX-License-Identifier: MIT OR Apache-2.0
//
// Copyright (c) 2018-2020 Andre Richter <andre.o.richter@gmail.com>
//! BSP Memory Management.
//--------------------------------------------------------------------------------------------------
// Public Definitions
//--------------------------------------------------------------------------------------------------
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: usize = 0x80_000;

2
05_safe_globals/src/_arch/aarch64/cpu.rs
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@ -25,7 +25,7 @@ pub unsafe extern "C" fn _start() -> ! {
// Expect the boot core to start in EL2.
if bsp::cpu::BOOT_CORE_ID == cpu::smp::core_id() {
SP.set(bsp::cpu::BOOT_CORE_STACK_START);
SP.set(bsp::memory::BOOT_CORE_STACK_START as u64);
runtime_init::runtime_init()
} else {
// If not core0, infinitely wait for events.

1
05_safe_globals/src/bsp/raspberrypi.rs
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@ -6,3 +6,4 @@
pub mod console;
pub mod cpu;
pub mod memory;

3
05_safe_globals/src/bsp/raspberrypi/cpu.rs
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@ -10,6 +10,3 @@
/// Used by `arch` code to find the early boot core.
pub const BOOT_CORE_ID: usize = 0;
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: u64 = 0x80_000;

12
05_safe_globals/src/bsp/raspberrypi/memory.rs
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@ -0,0 +1,12 @@
// SPDX-License-Identifier: MIT OR Apache-2.0
//
// Copyright (c) 2018-2020 Andre Richter <andre.o.richter@gmail.com>
//! BSP Memory Management.
//--------------------------------------------------------------------------------------------------
// Public Definitions
//--------------------------------------------------------------------------------------------------
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: usize = 0x80_000;

34
06_drivers_gpio_uart/README.md
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@ -850,31 +850,25 @@ diff -uNr 05_safe_globals/src/bsp/raspberrypi/driver.rs 06_drivers_gpio_uart/src
diff -uNr 05_safe_globals/src/bsp/raspberrypi/memory.rs 06_drivers_gpio_uart/src/bsp/raspberrypi/memory.rs
--- 05_safe_globals/src/bsp/raspberrypi/memory.rs
+++ 06_drivers_gpio_uart/src/bsp/raspberrypi/memory.rs
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0
+//
+// Copyright (c) 2018-2020 Andre Richter <andre.o.richter@gmail.com>
+
+//! BSP Memory Management.
+
+//--------------------------------------------------------------------------------------------------
+// Public Definitions
+//--------------------------------------------------------------------------------------------------
@@ -10,3 +10,30 @@
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: usize = 0x80_000;
+
+/// The board's memory map.
+#[rustfmt::skip]
+pub(super) mod map {
+ pub const GPIO_OFFSET: usize = 0x0020_0000;
+ pub const UART_OFFSET: usize = 0x0020_1000;
+ pub const GPIO_OFFSET: usize = 0x0020_0000;
+ pub const UART_OFFSET: usize = 0x0020_1000;
+
+ /// Physical devices.
+ #[cfg(feature = "bsp_rpi3")]
+ pub mod mmio {
+ use super::*;
+
+ pub const BASE: usize = 0x3F00_0000;
+ pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
+ pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
+ pub const BASE: usize = 0x3F00_0000;
+ pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
+ pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
+ }
+
+ /// Physical devices.
@ -882,21 +876,21 @@ diff -uNr 05_safe_globals/src/bsp/raspberrypi/memory.rs 06_drivers_gpio_uart/src
+ pub mod mmio {
+ use super::*;
+
+ pub const BASE: usize = 0xFE00_0000;
+ pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
+ pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
+ pub const BASE: usize = 0xFE00_0000;
+ pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
+ pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
+ }
+}
diff -uNr 05_safe_globals/src/bsp/raspberrypi.rs 06_drivers_gpio_uart/src/bsp/raspberrypi.rs
--- 05_safe_globals/src/bsp/raspberrypi.rs
+++ 06_drivers_gpio_uart/src/bsp/raspberrypi.rs
@@ -6,3 +6,33 @@
@@ -6,4 +6,33 @@
pub mod console;
pub mod cpu;
+pub mod driver;
+pub mod memory;
pub mod memory;
+
+//--------------------------------------------------------------------------------------------------
+// Global instances

2
06_drivers_gpio_uart/src/_arch/aarch64/cpu.rs
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@ -25,7 +25,7 @@ pub unsafe extern "C" fn _start() -> ! {
// Expect the boot core to start in EL2.
if bsp::cpu::BOOT_CORE_ID == cpu::smp::core_id() {
SP.set(bsp::cpu::BOOT_CORE_STACK_START);
SP.set(bsp::memory::BOOT_CORE_STACK_START as u64);
runtime_init::runtime_init()
} else {
// If not core0, infinitely wait for events.

3
06_drivers_gpio_uart/src/bsp/raspberrypi/cpu.rs
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@ -10,6 +10,3 @@
/// Used by `arch` code to find the early boot core.
pub const BOOT_CORE_ID: usize = 0;
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: u64 = 0x80_000;

19
06_drivers_gpio_uart/src/bsp/raspberrypi/memory.rs
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@ -8,20 +8,23 @@
// Public Definitions
//--------------------------------------------------------------------------------------------------
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: usize = 0x80_000;
/// The board's memory map.
#[rustfmt::skip]
pub(super) mod map {
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
/// Physical devices.
#[cfg(feature = "bsp_rpi3")]
pub mod mmio {
use super::*;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
}
/// Physical devices.
@ -29,8 +32,8 @@ pub(super) mod map {
pub mod mmio {
use super::*;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
}
}

31
07_uart_chainloader/README.md
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@ -187,7 +187,7 @@ diff -uNr 06_drivers_gpio_uart/src/_arch/aarch64/cpu.rs 07_uart_chainloader/src/
// Expect the boot core to start in EL2.
if bsp::cpu::BOOT_CORE_ID == cpu::smp::core_id() {
SP.set(bsp::cpu::BOOT_CORE_STACK_START);
SP.set(bsp::memory::BOOT_CORE_STACK_START as u64);
- runtime_init::runtime_init()
+ relocate::relocate_self::<u64>()
} else {
@ -246,17 +246,6 @@ diff -uNr 06_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 0
}
}
diff -uNr 06_drivers_gpio_uart/src/bsp/raspberrypi/cpu.rs 07_uart_chainloader/src/bsp/raspberrypi/cpu.rs
--- 06_drivers_gpio_uart/src/bsp/raspberrypi/cpu.rs
+++ 07_uart_chainloader/src/bsp/raspberrypi/cpu.rs
@@ -13,3 +13,6 @@
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: u64 = 0x80_000;
+
+/// The address on which the Raspberry firmware loads every binary by default.
+pub const BOARD_DEFAULT_LOAD_ADDRESS: usize = 0x80_000;
diff -uNr 06_drivers_gpio_uart/src/bsp/raspberrypi/link.ld 07_uart_chainloader/src/bsp/raspberrypi/link.ld
--- 06_drivers_gpio_uart/src/bsp/raspberrypi/link.ld
+++ 07_uart_chainloader/src/bsp/raspberrypi/link.ld
@ -289,6 +278,20 @@ diff -uNr 06_drivers_gpio_uart/src/bsp/raspberrypi/link.ld 07_uart_chainloader/s
/DISCARD/ : { *(.comment*) }
}
diff -uNr 06_drivers_gpio_uart/src/bsp/raspberrypi/memory.rs 07_uart_chainloader/src/bsp/raspberrypi/memory.rs
--- 06_drivers_gpio_uart/src/bsp/raspberrypi/memory.rs
+++ 07_uart_chainloader/src/bsp/raspberrypi/memory.rs
@@ -11,6 +11,9 @@
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: usize = 0x80_000;
+/// The address on which the Raspberry firmware loads every binary by default.
+pub const BOARD_DEFAULT_LOAD_ADDRESS: usize = 0x80_000;
+
/// The board's memory map.
#[rustfmt::skip]
pub(super) mod map {
diff -uNr 06_drivers_gpio_uart/src/console.rs 07_uart_chainloader/src/console.rs
--- 06_drivers_gpio_uart/src/console.rs
+++ 07_uart_chainloader/src/console.rs
@ -376,7 +379,7 @@ diff -uNr 06_drivers_gpio_uart/src/main.rs 07_uart_chainloader/src/main.rs
+ console().write_char('O');
+ console().write_char('K');
+
+ let kernel_addr: *mut u8 = bsp::cpu::BOARD_DEFAULT_LOAD_ADDRESS as *mut u8;
+ let kernel_addr: *mut u8 = bsp::memory::BOARD_DEFAULT_LOAD_ADDRESS as *mut u8;
+ unsafe {
+ // Read the kernel byte by byte.
+ for i in 0..size {
@ -450,7 +453,7 @@ diff -uNr 06_drivers_gpio_uart/src/relocate.rs 07_uart_chainloader/src/relocate.
+ let mut reloc_dst_addr: *mut T = binary_start_addr as *mut T;
+
+ // The address of where the previous firmware loaded us.
+ let mut src_addr: *const T = bsp::cpu::BOARD_DEFAULT_LOAD_ADDRESS as *const _;
+ let mut src_addr: *const T = bsp::memory::BOARD_DEFAULT_LOAD_ADDRESS as *const _;
+
+ // Copy the whole binary.
+ //

2
07_uart_chainloader/src/_arch/aarch64/cpu.rs
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@ -25,7 +25,7 @@ pub unsafe extern "C" fn _start() -> ! {
// Expect the boot core to start in EL2.
if bsp::cpu::BOOT_CORE_ID == cpu::smp::core_id() {
SP.set(bsp::cpu::BOOT_CORE_STACK_START);
SP.set(bsp::memory::BOOT_CORE_STACK_START as u64);
relocate::relocate_self::<u64>()
} else {
// If not core0, infinitely wait for events.

6
07_uart_chainloader/src/bsp/raspberrypi/cpu.rs
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@ -10,9 +10,3 @@
/// Used by `arch` code to find the early boot core.
pub const BOOT_CORE_ID: usize = 0;
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: u64 = 0x80_000;
/// The address on which the Raspberry firmware loads every binary by default.
pub const BOARD_DEFAULT_LOAD_ADDRESS: usize = 0x80_000;

22
07_uart_chainloader/src/bsp/raspberrypi/memory.rs
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@ -8,20 +8,26 @@
// Public Definitions
//--------------------------------------------------------------------------------------------------
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: usize = 0x80_000;
/// The address on which the Raspberry firmware loads every binary by default.
pub const BOARD_DEFAULT_LOAD_ADDRESS: usize = 0x80_000;
/// The board's memory map.
#[rustfmt::skip]
pub(super) mod map {
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
/// Physical devices.
#[cfg(feature = "bsp_rpi3")]
pub mod mmio {
use super::*;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
}
/// Physical devices.
@ -29,8 +35,8 @@ pub(super) mod map {
pub mod mmio {
use super::*;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
}
}

2
07_uart_chainloader/src/main.rs
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@ -177,7 +177,7 @@ fn kernel_main() -> ! {
console().write_char('O');
console().write_char('K');
let kernel_addr: *mut u8 = bsp::cpu::BOARD_DEFAULT_LOAD_ADDRESS as *mut u8;
let kernel_addr: *mut u8 = bsp::memory::BOARD_DEFAULT_LOAD_ADDRESS as *mut u8;
unsafe {
// Read the kernel byte by byte.
for i in 0..size {

2
07_uart_chainloader/src/relocate.rs
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@ -31,7 +31,7 @@ pub unsafe fn relocate_self<T>() -> ! {
let mut reloc_dst_addr: *mut T = binary_start_addr as *mut T;
// The address of where the previous firmware loaded us.
let mut src_addr: *const T = bsp::cpu::BOARD_DEFAULT_LOAD_ADDRESS as *const _;
let mut src_addr: *const T = bsp::memory::BOARD_DEFAULT_LOAD_ADDRESS as *const _;
// Copy the whole binary.
//

31
08_timestamps/README.md
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@ -111,7 +111,7 @@ diff -uNr 07_uart_chainloader/src/_arch/aarch64/cpu.rs 08_timestamps/src/_arch/a
// Expect the boot core to start in EL2.
if bsp::cpu::BOOT_CORE_ID == cpu::smp::core_id() {
SP.set(bsp::cpu::BOOT_CORE_STACK_START);
SP.set(bsp::memory::BOOT_CORE_STACK_START as u64);
- relocate::relocate_self::<u64>()
+ runtime_init::runtime_init()
} else {
@ -249,17 +249,6 @@ diff -uNr 07_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 08
}
diff -uNr 07_uart_chainloader/src/bsp/raspberrypi/cpu.rs 08_timestamps/src/bsp/raspberrypi/cpu.rs
--- 07_uart_chainloader/src/bsp/raspberrypi/cpu.rs
+++ 08_timestamps/src/bsp/raspberrypi/cpu.rs
@@ -13,6 +13,3 @@
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: u64 = 0x80_000;
-
-/// The address on which the Raspberry firmware loads every binary by default.
-pub const BOARD_DEFAULT_LOAD_ADDRESS: usize = 0x80_000;
diff -uNr 07_uart_chainloader/src/bsp/raspberrypi/link.ld 08_timestamps/src/bsp/raspberrypi/link.ld
--- 07_uart_chainloader/src/bsp/raspberrypi/link.ld
+++ 08_timestamps/src/bsp/raspberrypi/link.ld
@ -292,6 +281,20 @@ diff -uNr 07_uart_chainloader/src/bsp/raspberrypi/link.ld 08_timestamps/src/bsp/
/DISCARD/ : { *(.comment*) }
}
diff -uNr 07_uart_chainloader/src/bsp/raspberrypi/memory.rs 08_timestamps/src/bsp/raspberrypi/memory.rs
--- 07_uart_chainloader/src/bsp/raspberrypi/memory.rs
+++ 08_timestamps/src/bsp/raspberrypi/memory.rs
@@ -11,9 +11,6 @@
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: usize = 0x80_000;
-/// The address on which the Raspberry firmware loads every binary by default.
-pub const BOARD_DEFAULT_LOAD_ADDRESS: usize = 0x80_000;
-
/// The board's memory map.
#[rustfmt::skip]
pub(super) mod map {
diff -uNr 07_uart_chainloader/src/main.rs 08_timestamps/src/main.rs
--- 07_uart_chainloader/src/main.rs
+++ 08_timestamps/src/main.rs
@ -368,7 +371,7 @@ diff -uNr 07_uart_chainloader/src/main.rs 08_timestamps/src/main.rs
- console().write_char('O');
- console().write_char('K');
-
- let kernel_addr: *mut u8 = bsp::cpu::BOARD_DEFAULT_LOAD_ADDRESS as *mut u8;
- let kernel_addr: *mut u8 = bsp::memory::BOARD_DEFAULT_LOAD_ADDRESS as *mut u8;
- unsafe {
- // Read the kernel byte by byte.
- for i in 0..size {
@ -517,7 +520,7 @@ diff -uNr 07_uart_chainloader/src/relocate.rs 08_timestamps/src/relocate.rs
- let mut reloc_dst_addr: *mut T = binary_start_addr as *mut T;
-
- // The address of where the previous firmware loaded us.
- let mut src_addr: *const T = bsp::cpu::BOARD_DEFAULT_LOAD_ADDRESS as *const _;
- let mut src_addr: *const T = bsp::memory::BOARD_DEFAULT_LOAD_ADDRESS as *const _;
-
- // Copy the whole binary.
- //

2
08_timestamps/src/_arch/aarch64/cpu.rs
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@ -25,7 +25,7 @@ pub unsafe extern "C" fn _start() -> ! {
// Expect the boot core to start in EL2.
if bsp::cpu::BOOT_CORE_ID == cpu::smp::core_id() {
SP.set(bsp::cpu::BOOT_CORE_STACK_START);
SP.set(bsp::memory::BOOT_CORE_STACK_START as u64);
runtime_init::runtime_init()
} else {
// If not core0, infinitely wait for events.

3
08_timestamps/src/bsp/raspberrypi/cpu.rs
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@ -10,6 +10,3 @@
/// Used by `arch` code to find the early boot core.
pub const BOOT_CORE_ID: usize = 0;
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: u64 = 0x80_000;

19
08_timestamps/src/bsp/raspberrypi/memory.rs
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@ -8,20 +8,23 @@
// Public Definitions
//--------------------------------------------------------------------------------------------------
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: usize = 0x80_000;
/// The board's memory map.
#[rustfmt::skip]
pub(super) mod map {
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
/// Physical devices.
#[cfg(feature = "bsp_rpi3")]
pub mod mmio {
use super::*;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
}
/// Physical devices.
@ -29,8 +32,8 @@ pub(super) mod map {
pub mod mmio {
use super::*;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
}
}

2
09_hw_debug_JTAG/src/_arch/aarch64/cpu.rs
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@ -25,7 +25,7 @@ pub unsafe extern "C" fn _start() -> ! {
// Expect the boot core to start in EL2.
if bsp::cpu::BOOT_CORE_ID == cpu::smp::core_id() {
SP.set(bsp::cpu::BOOT_CORE_STACK_START);
SP.set(bsp::memory::BOOT_CORE_STACK_START as u64);
runtime_init::runtime_init()
} else {
// If not core0, infinitely wait for events.

3
09_hw_debug_JTAG/src/bsp/raspberrypi/cpu.rs
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@ -10,6 +10,3 @@
/// Used by `arch` code to find the early boot core.
pub const BOOT_CORE_ID: usize = 0;
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: u64 = 0x80_000;

19
09_hw_debug_JTAG/src/bsp/raspberrypi/memory.rs
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@ -8,20 +8,23 @@
// Public Definitions
//--------------------------------------------------------------------------------------------------
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: usize = 0x80_000;
/// The board's memory map.
#[rustfmt::skip]
pub(super) mod map {
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
/// Physical devices.
#[cfg(feature = "bsp_rpi3")]
pub mod mmio {
use super::*;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
}
/// Physical devices.
@ -29,8 +32,8 @@ pub(super) mod map {
pub mod mmio {
use super::*;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
}
}

4
10_privilege_level/README.md
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@ -233,7 +233,7 @@ diff -uNr 09_hw_debug_JTAG/src/_arch/aarch64/cpu.rs 10_privilege_level/src/_arch
-
// Expect the boot core to start in EL2.
- if bsp::cpu::BOOT_CORE_ID == cpu::smp::core_id() {
- SP.set(bsp::cpu::BOOT_CORE_STACK_START);
- SP.set(bsp::memory::BOOT_CORE_STACK_START as u64);
- runtime_init::runtime_init()
+ if (bsp::cpu::BOOT_CORE_ID == cpu::smp::core_id())
+ && (CurrentEL.get() == CurrentEL::EL::EL2.value)
@ -281,7 +281,7 @@ diff -uNr 09_hw_debug_JTAG/src/_arch/aarch64/cpu.rs 10_privilege_level/src/_arch
+ ELR_EL2.set(runtime_init::runtime_init as *const () as u64);
+
+ // Set up SP_EL1 (stack pointer), which will be used by EL1 once we "return" to it.
+ SP_EL1.set(bsp::cpu::BOOT_CORE_STACK_START);
+ SP_EL1.set(bsp::memory::BOOT_CORE_STACK_START as u64);
+
+ // Use `eret` to "return" to EL1. This results in execution of runtime_init() in EL1.
+ asm::eret()

2
10_privilege_level/src/_arch/aarch64/cpu.rs
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@ -68,7 +68,7 @@ unsafe fn el2_to_el1_transition() -> ! {
ELR_EL2.set(runtime_init::runtime_init as *const () as u64);
// Set up SP_EL1 (stack pointer), which will be used by EL1 once we "return" to it.
SP_EL1.set(bsp::cpu::BOOT_CORE_STACK_START);
SP_EL1.set(bsp::memory::BOOT_CORE_STACK_START as u64);
// Use `eret` to "return" to EL1. This results in execution of runtime_init() in EL1.
asm::eret()

3
10_privilege_level/src/bsp/raspberrypi/cpu.rs
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@ -10,6 +10,3 @@
/// Used by `arch` code to find the early boot core.
pub const BOOT_CORE_ID: usize = 0;
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: u64 = 0x80_000;

19
10_privilege_level/src/bsp/raspberrypi/memory.rs
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@ -8,20 +8,23 @@
// Public Definitions
//--------------------------------------------------------------------------------------------------
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: usize = 0x80_000;
/// The board's memory map.
#[rustfmt::skip]
pub(super) mod map {
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
/// Physical devices.
#[cfg(feature = "bsp_rpi3")]
pub mod mmio {
use super::*;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
}
/// Physical devices.
@ -29,8 +32,8 @@ pub(super) mod map {
pub mod mmio {
use super::*;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
}
}

28
11_virtual_memory/README.md
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@ -755,28 +755,28 @@ diff -uNr 10_privilege_level/src/bsp/raspberrypi/memory.rs 11_virtual_memory/src
//--------------------------------------------------------------------------------------------------
// Public Definitions
//--------------------------------------------------------------------------------------------------
@@ -11,6 +13,8 @@
@@ -14,6 +16,8 @@
/// The board's memory map.
#[rustfmt::skip]
pub(super) mod map {
+ pub const END_INCLUSIVE: usize = 0xFFFF_FFFF;
+ pub const END_INCLUSIVE: usize = 0xFFFF_FFFF;
+
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
@@ -22,6 +26,7 @@
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
+ pub const END_INCLUSIVE: usize = 0x4000_FFFF;
@@ -25,6 +29,7 @@
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
+ pub const END_INCLUSIVE: usize = 0x4000_FFFF;
}
/// Physical devices.
@@ -32,5 +37,6 @@
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
+ pub const END_INCLUSIVE: usize = 0xFF84_FFFF;
@@ -35,5 +40,6 @@
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
+ pub const END_INCLUSIVE: usize = 0xFF84_FFFF;
}
}

2
11_virtual_memory/src/_arch/aarch64/cpu.rs
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@ -68,7 +68,7 @@ unsafe fn el2_to_el1_transition() -> ! {
ELR_EL2.set(runtime_init::runtime_init as *const () as u64);
// Set up SP_EL1 (stack pointer), which will be used by EL1 once we "return" to it.
SP_EL1.set(bsp::cpu::BOOT_CORE_STACK_START);
SP_EL1.set(bsp::memory::BOOT_CORE_STACK_START as u64);
// Use `eret` to "return" to EL1. This results in execution of runtime_init() in EL1.
asm::eret()

3
11_virtual_memory/src/bsp/raspberrypi/cpu.rs
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@ -10,6 +10,3 @@
/// Used by `arch` code to find the early boot core.
pub const BOOT_CORE_ID: usize = 0;
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: u64 = 0x80_000;

25
11_virtual_memory/src/bsp/raspberrypi/memory.rs
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@ -10,23 +10,26 @@ pub mod mmu;
// Public Definitions
//--------------------------------------------------------------------------------------------------
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: usize = 0x80_000;
/// The board's memory map.
#[rustfmt::skip]
pub(super) mod map {
pub const END_INCLUSIVE: usize = 0xFFFF_FFFF;
pub const END_INCLUSIVE: usize = 0xFFFF_FFFF;
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
/// Physical devices.
#[cfg(feature = "bsp_rpi3")]
pub mod mmio {
use super::*;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const END_INCLUSIVE: usize = 0x4000_FFFF;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const END_INCLUSIVE: usize = 0x4000_FFFF;
}
/// Physical devices.
@ -34,9 +37,9 @@ pub(super) mod map {
pub mod mmio {
use super::*;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const END_INCLUSIVE: usize = 0xFF84_FFFF;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const END_INCLUSIVE: usize = 0xFF84_FFFF;
}
}

2
12_exceptions_part1_groundwork/src/_arch/aarch64/cpu.rs
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@ -68,7 +68,7 @@ unsafe fn el2_to_el1_transition() -> ! {
ELR_EL2.set(runtime_init::runtime_init as *const () as u64);
// Set up SP_EL1 (stack pointer), which will be used by EL1 once we "return" to it.
SP_EL1.set(bsp::cpu::BOOT_CORE_STACK_START);
SP_EL1.set(bsp::memory::BOOT_CORE_STACK_START as u64);
// Use `eret` to "return" to EL1. This results in execution of runtime_init() in EL1.
asm::eret()

3
12_exceptions_part1_groundwork/src/bsp/raspberrypi/cpu.rs
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@ -10,6 +10,3 @@
/// Used by `arch` code to find the early boot core.
pub const BOOT_CORE_ID: usize = 0;
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: u64 = 0x80_000;

25
12_exceptions_part1_groundwork/src/bsp/raspberrypi/memory.rs
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@ -10,23 +10,26 @@ pub mod mmu;
// Public Definitions
//--------------------------------------------------------------------------------------------------
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: usize = 0x80_000;
/// The board's memory map.
#[rustfmt::skip]
pub(super) mod map {
pub const END_INCLUSIVE: usize = 0xFFFF_FFFF;
pub const END_INCLUSIVE: usize = 0xFFFF_FFFF;
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
/// Physical devices.
#[cfg(feature = "bsp_rpi3")]
pub mod mmio {
use super::*;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const END_INCLUSIVE: usize = 0x4000_FFFF;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const END_INCLUSIVE: usize = 0x4000_FFFF;
}
/// Physical devices.
@ -34,9 +37,9 @@ pub(super) mod map {
pub mod mmio {
use super::*;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const END_INCLUSIVE: usize = 0xFF84_FFFF;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const END_INCLUSIVE: usize = 0xFF84_FFFF;
}
}

2
13_integrated_testing/src/_arch/aarch64/cpu.rs
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@ -68,7 +68,7 @@ unsafe fn el2_to_el1_transition() -> ! {
ELR_EL2.set(runtime_init::runtime_init as *const () as u64);
// Set up SP_EL1 (stack pointer), which will be used by EL1 once we "return" to it.
SP_EL1.set(bsp::cpu::BOOT_CORE_STACK_START);
SP_EL1.set(bsp::memory::BOOT_CORE_STACK_START as u64);
// Use `eret` to "return" to EL1. This results in execution of runtime_init() in EL1.
asm::eret()

3
13_integrated_testing/src/bsp/raspberrypi/cpu.rs
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@ -10,6 +10,3 @@
/// Used by `arch` code to find the early boot core.
pub const BOOT_CORE_ID: usize = 0;
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: u64 = 0x80_000;

25
13_integrated_testing/src/bsp/raspberrypi/memory.rs
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@ -10,23 +10,26 @@ pub mod mmu;
// Public Definitions
//--------------------------------------------------------------------------------------------------
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: usize = 0x80_000;
/// The board's memory map.
#[rustfmt::skip]
pub(super) mod map {
pub const END_INCLUSIVE: usize = 0xFFFF_FFFF;
pub const END_INCLUSIVE: usize = 0xFFFF_FFFF;
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
/// Physical devices.
#[cfg(feature = "bsp_rpi3")]
pub mod mmio {
use super::*;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const END_INCLUSIVE: usize = 0x4000_FFFF;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const END_INCLUSIVE: usize = 0x4000_FFFF;
}
/// Physical devices.
@ -34,9 +37,9 @@ pub(super) mod map {
pub mod mmio {
use super::*;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const END_INCLUSIVE: usize = 0xFF84_FFFF;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const END_INCLUSIVE: usize = 0xFF84_FFFF;
}
}

74
14_exceptions_part2_peripheral_IRQs/README.md
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@ -2063,17 +2063,6 @@ diff -uNr 13_integrated_testing/src/bsp/device_driver.rs 14_exceptions_part2_per
#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))]
pub use bcm::*;
diff -uNr 13_integrated_testing/src/bsp/raspberrypi/cpu.rs 14_exceptions_part2_peripheral_IRQs/src/bsp/raspberrypi/cpu.rs
--- 13_integrated_testing/src/bsp/raspberrypi/cpu.rs
+++ 14_exceptions_part2_peripheral_IRQs/src/bsp/raspberrypi/cpu.rs
@@ -13,3 +13,6 @@
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: u64 = 0x80_000;
+
+/// The number of processor cores.
+pub const NUM_CORES: usize = 4;
diff -uNr 13_integrated_testing/src/bsp/raspberrypi/driver.rs 14_exceptions_part2_peripheral_IRQs/src/bsp/raspberrypi/driver.rs
--- 13_integrated_testing/src/bsp/raspberrypi/driver.rs
+++ 14_exceptions_part2_peripheral_IRQs/src/bsp/raspberrypi/driver.rs
@ -2156,24 +2145,50 @@ diff -uNr 13_integrated_testing/src/bsp/raspberrypi/exception.rs 14_exceptions_p
diff -uNr 13_integrated_testing/src/bsp/raspberrypi/memory.rs 14_exceptions_part2_peripheral_IRQs/src/bsp/raspberrypi/memory.rs
--- 13_integrated_testing/src/bsp/raspberrypi/memory.rs
+++ 14_exceptions_part2_peripheral_IRQs/src/bsp/raspberrypi/memory.rs
@@ -24,8 +24,10 @@
@@ -16,20 +16,22 @@
/// The board's memory map.
#[rustfmt::skip]
pub(super) mod map {
- pub const END_INCLUSIVE: usize = 0xFFFF_FFFF;
+ pub const END_INCLUSIVE: usize = 0xFFFF_FFFF;
- pub const GPIO_OFFSET: usize = 0x0020_0000;
- pub const UART_OFFSET: usize = 0x0020_1000;
+ pub const GPIO_OFFSET: usize = 0x0020_0000;
+ pub const UART_OFFSET: usize = 0x0020_1000;
/// Physical devices.
#[cfg(feature = "bsp_rpi3")]
pub mod mmio {
use super::*;
pub const BASE: usize = 0x3F00_0000;
- pub const BASE: usize = 0x3F00_0000;
- pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
- pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
- pub const END_INCLUSIVE: usize = 0x4000_FFFF;
+ pub const BASE: usize = 0x3F00_0000;
+ pub const PERIPHERAL_INTERRUPT_CONTROLLER_BASE: usize = BASE + 0x0000_B200;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
+ pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
+ pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
+ pub const LOCAL_INTERRUPT_CONTROLLER_BASE: usize = 0x4000_0000;
pub const END_INCLUSIVE: usize = 0x4000_FFFF;
+ pub const END_INCLUSIVE: usize = 0x4000_FFFF;
}
@@ -37,6 +39,8 @@
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
/// Physical devices.
@@ -37,9 +39,11 @@
pub mod mmio {
use super::*;
- pub const BASE: usize = 0xFE00_0000;
- pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
- pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
- pub const END_INCLUSIVE: usize = 0xFF84_FFFF;
+ pub const BASE: usize = 0xFE00_0000;
+ pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
+ pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
+ pub const GICD_BASE: usize = 0xFF84_1000;
+ pub const GICC_BASE: usize = 0xFF84_2000;
pub const END_INCLUSIVE: usize = 0xFF84_FFFF;
+ pub const END_INCLUSIVE: usize = 0xFF84_FFFF;
}
}
@ -2217,6 +2232,23 @@ diff -uNr 13_integrated_testing/src/bsp/raspberrypi.rs 14_exceptions_part2_perip
//--------------------------------------------------------------------------------------------------
// Public Code
diff -uNr 13_integrated_testing/src/common.rs 14_exceptions_part2_peripheral_IRQs/src/common.rs
--- 13_integrated_testing/src/common.rs
+++ 14_exceptions_part2_peripheral_IRQs/src/common.rs
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0
+//
+// Copyright (c) 2020 Andre Richter <andre.o.richter@gmail.com>
+
+//! General purpose stuff.
+
+/// Downard alignment of the input data.
+pub const fn align_down(value: u64, align: u64) -> u64 {
+ assert!(align.is_power_of_two());
+
+ value & (!(align - 1))
+}
diff -uNr 13_integrated_testing/src/driver.rs 14_exceptions_part2_peripheral_IRQs/src/driver.rs
--- 13_integrated_testing/src/driver.rs
+++ 14_exceptions_part2_peripheral_IRQs/src/driver.rs

2
14_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/cpu.rs
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@ -68,7 +68,7 @@ unsafe fn el2_to_el1_transition() -> ! {
ELR_EL2.set(runtime_init::runtime_init as *const () as u64);
// Set up SP_EL1 (stack pointer), which will be used by EL1 once we "return" to it.
SP_EL1.set(bsp::cpu::BOOT_CORE_STACK_START);
SP_EL1.set(bsp::memory::BOOT_CORE_STACK_START as u64);
// Use `eret` to "return" to EL1. This results in execution of runtime_init() in EL1.
asm::eret()

6
14_exceptions_part2_peripheral_IRQs/src/bsp/raspberrypi/cpu.rs
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@ -10,9 +10,3 @@
/// Used by `arch` code to find the early boot core.
pub const BOOT_CORE_ID: usize = 0;
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: u64 = 0x80_000;
/// The number of processor cores.
pub const NUM_CORES: usize = 4;

3
14_exceptions_part2_peripheral_IRQs/src/bsp/raspberrypi/memory.rs
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@ -10,6 +10,9 @@ pub mod mmu;
// Public Definitions
//--------------------------------------------------------------------------------------------------
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: usize = 0x80_000;
/// The board's memory map.
#[rustfmt::skip]
pub(super) mod map {

13
X1_JTAG_boot/.vscode/settings.json vendored
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@ -4,10 +4,11 @@
100
],
"rust-analyzer.checkOnSave.overrideCommand": [
"cargo",
"check",
"--message-format=json",
"--target=aarch64-unknown-none-softfloat",
"--features=bsp_rpi3"
"make",
"check"
],
"rust-analyzer.cargo.target": "aarch64-unknown-none-softfloat",
"rust-analyzer.cargo.features": [
"bsp_rpi3"
]
}
}

2
X1_JTAG_boot/Makefile
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@ -98,7 +98,7 @@ clean:
rm -rf target $(KERNEL_BIN)
readelf: $(KERNEL_ELF)
readelf -a $(KERNEL_ELF)
readelf --headers $(KERNEL_ELF)
objdump: $(KERNEL_ELF)
rust-objdump --arch-name aarch64 --disassemble --demangle --no-show-raw-insn \

BIN
X1_JTAG_boot/jtag_boot_rpi3.img
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BIN
X1_JTAG_boot/jtag_boot_rpi4.img
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2
X1_JTAG_boot/src/_arch/aarch64/cpu.rs
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@ -25,7 +25,7 @@ pub unsafe extern "C" fn _start() -> ! {
// Expect the boot core to start in EL2.
if bsp::cpu::BOOT_CORE_ID == cpu::smp::core_id() {
SP.set(bsp::cpu::BOOT_CORE_STACK_START);
SP.set(bsp::memory::BOOT_CORE_STACK_START as u64);
runtime_init::runtime_init()
} else {
// If not core0, infinitely wait for events.

17
X1_JTAG_boot/src/bsp/raspberrypi.rs
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@ -19,20 +19,3 @@ static GPIO: device_driver::GPIO =
static PL011_UART: device_driver::PL011Uart =
unsafe { device_driver::PL011Uart::new(memory::map::mmio::PL011_UART_BASE) };
//--------------------------------------------------------------------------------------------------
// Public Code
//--------------------------------------------------------------------------------------------------
/// Board identification.
pub fn board_name() -> &'static str {
#[cfg(feature = "bsp_rpi3")]
{
"Raspberry Pi 3"
}
#[cfg(feature = "bsp_rpi4")]
{
"Raspberry Pi 4"
}
}

3
X1_JTAG_boot/src/bsp/raspberrypi/cpu.rs
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@ -10,6 +10,3 @@
/// Used by `arch` code to find the early boot core.
pub const BOOT_CORE_ID: usize = 0;
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: u64 = 0x80_000;

19
X1_JTAG_boot/src/bsp/raspberrypi/memory.rs
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@ -8,20 +8,23 @@
// Public Definitions
//--------------------------------------------------------------------------------------------------
/// The early boot core's stack address.
pub const BOOT_CORE_STACK_START: usize = 0x80_000;
/// The board's memory map.
#[rustfmt::skip]
pub(super) mod map {
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART_OFFSET: usize = 0x0020_1000;
/// Physical devices.
#[cfg(feature = "bsp_rpi3")]
pub mod mmio {
use super::*;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const BASE: usize = 0x3F00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
}
/// Physical devices.
@ -29,8 +32,8 @@ pub(super) mod map {
pub mod mmio {
use super::*;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
pub const BASE: usize = 0xFE00_0000;
pub const GPIO_BASE: usize = BASE + GPIO_OFFSET;
pub const PL011_UART_BASE: usize = BASE + UART_OFFSET;
}
}

17
X1_JTAG_boot/src/main.rs
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@ -110,19 +110,18 @@
#![no_std]
// `mod cpu` provides the `_start()` function, the first function to run. `_start()` then calls
// `runtime_init()`, which jumps to `kernel_init()` (defined in `main.rs`).
// `runtime_init()`, which jumps to `kernel_init()`.
mod bsp;
mod console;
mod cpu;
mod driver;
mod memory;
mod panic_wait;
mod print;
mod runtime_init;
mod synchronization;
pub mod bsp;
pub mod console;
pub mod cpu;
pub mod driver;
pub mod memory;
pub mod print;
pub mod time;
mod time;
/// Early init code.
///

9
X1_JTAG_boot/src/synchronization.rs
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@ -16,10 +16,8 @@ pub mod interface {
/// Any object implementing this trait guarantees exclusive access to the data contained within
/// the Mutex for the duration of the provided closure.
///
/// The trait follows the [Rust embedded WG's
/// proposal](https://github.com/korken89/wg/blob/master/rfcs/0377-mutex-trait.md) and therefore
/// provides some goodness such as [deadlock
/// prevention](https://github.com/korken89/wg/blob/master/rfcs/0377-mutex-trait.md#design-decisions-and-compatibility).
/// The trait follows the [Rust embedded WG's proposal] and therefore provides some goodness
/// such as [deadlock prevention].
///
/// # Example
///
@ -27,6 +25,9 @@ pub mod interface {
/// best implemented **for a reference to a container struct**, and has a usage pattern that
/// might feel strange at first:
///
/// [Rust embedded WG's proposal]: https://github.com/rust-embedded/wg/blob/master/rfcs/0377-mutex-trait.md
/// [deadlock prevention]: https://github.com/rust-embedded/wg/blob/master/rfcs/0377-mutex-trait.md#design-decisions-and-compatibility
///
/// ```
/// static MUT: Mutex<RefCell<i32>> = Mutex::new(RefCell::new(0));
///

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