Add tutorial 0D_cache_performance
Andre Richter
6 years ago
parent
bf2a1fff7e
commit
c65e2e56cd
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[target.aarch64-unknown-none]
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rustflags = [
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"-C", "link-arg=-Tlink.ld",
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"-C", "target-feature=-fp-armv8",
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"-C", "target-cpu=cortex-a53",
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]
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@ -0,0 +1,55 @@
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[[package]]
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name = "cortex-a"
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version = "2.2.1"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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"register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "kernel8"
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version = "0.1.0"
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dependencies = [
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"cortex-a 2.2.1 (registry+https://github.com/rust-lang/crates.io-index)",
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"raspi3_boot 0.1.0",
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"register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "panic-abort"
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version = "0.2.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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name = "r0"
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version = "0.2.2"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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name = "raspi3_boot"
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version = "0.1.0"
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dependencies = [
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"cortex-a 2.2.1 (registry+https://github.com/rust-lang/crates.io-index)",
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"panic-abort 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "register"
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version = "0.2.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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"tock-registers 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "tock-registers"
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version = "0.2.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[metadata]
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"checksum cortex-a 2.2.1 (registry+https://github.com/rust-lang/crates.io-index)" = "fe913628f34718bc9e7d0d07e13ca1374638f64f0edc6eb063ec8abe581d395d"
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"checksum panic-abort 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)" = "6bc796c620f27056d4ffe7c558533fd67ae5af0fd8e919fbe38de803368af73e"
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"checksum r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)" = "e2a38df5b15c8d5c7e8654189744d8e396bddc18ad48041a500ce52d6948941f"
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"checksum register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)" = "157a11ac0b1882ff4a527a92f911dd288df17367faaaa0c36f188cd61ec36fc1"
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"checksum tock-registers 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)" = "3a385d94f3f62e60445a0adb9ff8d9621faa272234530d4c0f848ec98f88e316"
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@ -0,0 +1,12 @@
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[package]
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name = "kernel8"
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version = "0.1.0"
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authors = ["Andre Richter <andre.o.richter@gmail.com>"]
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[dependencies]
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raspi3_boot = { path = "raspi3_boot" }
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cortex-a = "2.2.1"
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register = "0.2.0"
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[package.metadata.cargo-xbuild]
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sysroot_path = "../xbuild_sysroot"
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#
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# MIT License
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#
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# Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
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# copies of the Software, and to permit persons to whom the Software is
|
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in all
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# copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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# SOFTWARE.
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#
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TARGET = aarch64-unknown-none
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OBJCOPY = cargo objcopy --
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OBJCOPY_PARAMS = --strip-all -O binary
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UTILS_CONTAINER = andrerichter/raspi3-utils
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DOCKER_CMD = docker run -it --rm -v $(shell pwd):/work -w /work
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DOCKER_TTY = --privileged -v /dev:/dev
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QEMU_CMD = qemu-system-aarch64 -M raspi3 -kernel kernel8.img
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RASPBOOT_CMD = raspbootcom /dev/ttyUSB0 kernel8.img
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all: clean kernel8.img
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target/$(TARGET)/debug/kernel8: src/main.rs
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cargo xbuild --target=$(TARGET)
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cp $@ .
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target/$(TARGET)/release/kernel8: src/main.rs
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cargo xbuild --target=$(TARGET) --release
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cp $@ .
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ifeq ($(DEBUG),1)
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kernel8: target/$(TARGET)/debug/kernel8
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else
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kernel8: target/$(TARGET)/release/kernel8
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endif
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kernel8.img: kernel8
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$(OBJCOPY) $(OBJCOPY_PARAMS) $< kernel8.img
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qemu: all
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$(DOCKER_CMD) $(UTILS_CONTAINER) $(QEMU_CMD) -serial stdio
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raspboot: all
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$(DOCKER_CMD) $(DOCKER_TTY) $(UTILS_CONTAINER) $(RASPBOOT_CMD)
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clippy:
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cargo xclippy --target=$(TARGET)
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clean:
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cargo clean
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rm -f kernel8
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# Tutorial 0D - Cache Performance
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Now that we finally have virtual memory capabilities available, we also have
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fine grained control over `cacheability`. You've caught a glimpse already in the
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last tutorial, where we used page table entries to reference the `MAIR_EL1`
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register to indicate the cacheability of a page or block.
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Unfortunately, for the user it is often hard to grasp the advantage of caching
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in early stages of OS or bare-metal software development. This tutorial is a
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short interlude that tries to give you a feeling of what caching can do for
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performance.
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## Benchmark
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Let's write a tiny, arbitrary micro-benchmark to showcase the performance of
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operating on the same DRAM with caching enabled and disabled.
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### mmu.rs
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Therefore, we will map the same physical memory via two different virtual
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addresses. We set up our pagetables such that the virtual address `0x200000`
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points to the physical DRAM at `0x400000`, and we configure it as
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`non-cacheable` in the page tables.
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We are still using a `2 MiB` granule, and set up the next block, which starts at
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virtual `0x400000`, to point at physical `0x400000` (this is an identity mapped
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block). This time, the block is configured as cacheable.
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### benchmark.rs
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We write a little function that iteratively reads memory of five times the size
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of a `cacheline`, in steps of 8 bytes, aka one processor register at a time. We
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read the value, add 1, and write it back. This whole process is repeated
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`100_000` times.
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### main.rs
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The benchmark function is called twice. Once for the cacheable and once for the
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non-cacheable virtual addresses. Remember that both virtual addresses point to
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the _same_ physical DRAM, so the difference in time that we will see will
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showcase how much faster it is to operate on DRAM with caching enabled.
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## Results
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On my Raspberry, I get the following results:
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```text
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Benchmarking non-cacheable DRAM modifications at virtual 0x00200000, physical 0x00400000:
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664 miliseconds.
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Benchmarking cacheable DRAM modifications at virtual 0x00400000, physical 0x00400000:
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148 miliseconds.
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With caching, the function is 348% faster!
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```
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Impressive, isn't it?
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/*
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* MIT License
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*
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* Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
|
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
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* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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||||
*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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ENTRY(_boot_cores);
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SECTIONS
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{
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. = 0x80000; /* This is already 4KiB aligned */
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__ro_start = .;
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.text :
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{
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KEEP(*(.text.boot)) *(.text .text.*)
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}
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.rodata :
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{
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*(.rodata .rodata.*)
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}
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. = ALIGN(4096); /* Fill up to 4KiB */
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__ro_end = .;
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.data :
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{
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*(.data .data.*)
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}
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.bss ALIGN(8):
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{
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__bss_start = .;
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*(.bss .bss.*)
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*(COMMON)
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__bss_end = .;
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}
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/DISCARD/ : { *(.comment) *(.gnu*) *(.note*) *(.eh_frame*) }
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}
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[package]
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name = "raspi3_boot"
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version = "0.1.0"
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authors = ["Andre Richter <andre.o.richter@gmail.com>"]
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[dependencies]
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cortex-a = "2.2.1"
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panic-abort = "0.2.0"
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r0 = "0.2.2"
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@ -0,0 +1,131 @@
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/*
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* MIT License
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*
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* Copyright (c) 2018 Jorge Aparicio
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* Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
|
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#![deny(missing_docs)]
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#![deny(warnings)]
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#![no_std]
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//! Low-level boot of the Raspberry's processor
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extern crate cortex_a;
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extern crate panic_abort;
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extern crate r0;
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#[macro_export]
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macro_rules! entry {
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($path:path) => {
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#[export_name = "main"]
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pub unsafe fn __main() -> ! {
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// type check the given path
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let f: fn() -> ! = $path;
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f()
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}
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};
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}
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/// Reset function.
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///
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/// Initializes the bss section before calling into the user's `main()`.
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unsafe fn reset() -> ! {
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extern "C" {
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// Boundaries of the .bss section, provided by the linker script
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static mut __bss_start: u64;
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static mut __bss_end: u64;
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}
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// Zeroes the .bss section
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r0::zero_bss(&mut __bss_start, &mut __bss_end);
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extern "Rust" {
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fn main() -> !;
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}
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main()
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}
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/// Prepare and execute transition from EL2 to EL1.
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#[inline]
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fn setup_and_enter_el1_from_el2() -> ! {
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use cortex_a::{asm, regs::*};
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// Enable timer counter registers for EL1
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CNTHCTL_EL2.write(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET);
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// No offset for reading the counters
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CNTVOFF_EL2.set(0);
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// Set EL1 execution state to AArch64
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// TODO: Explain the SWIO bit
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HCR_EL2.write(HCR_EL2::RW::EL1IsAarch64 + HCR_EL2::SWIO::SET);
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// Set up a simulated exception return.
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//
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// First, fake a saved program status, where all interrupts were
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// masked and SP_EL0 was used as a stack pointer.
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SPSR_EL2.write(
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SPSR_EL2::D::Masked
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+ SPSR_EL2::A::Masked
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+ SPSR_EL2::I::Masked
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+ SPSR_EL2::F::Masked
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+ SPSR_EL2::M::EL1t,
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);
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// Second, let the link register point to reset().
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ELR_EL2.set(reset as *const () as u64);
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// Set up SP_EL0 (stack pointer), which will be used by EL1 once
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// we "return" to it.
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SP_EL0.set(0x80_000);
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// Use `eret` to "return" to EL1. This will result in execution of
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// `reset()` in EL1.
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asm::eret()
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}
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/// Entrypoint of the processor.
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///
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/// Parks all cores except core0 and checks if we started in EL2. If
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/// so, proceeds with setting up EL1.
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#[link_section = ".text.boot"]
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#[no_mangle]
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pub unsafe extern "C" fn _boot_cores() -> ! {
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use cortex_a::{asm, regs::*};
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const CORE_0: u64 = 0;
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const CORE_MASK: u64 = 0x3;
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const EL2: u32 = CurrentEL::EL::EL2.value;
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if let CORE_0 = MPIDR_EL1.get() & CORE_MASK {
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if let EL2 = CurrentEL.get() {
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setup_and_enter_el1_from_el2()
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}
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}
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// if not core0 or EL != 2, infinitely wait for events
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loop {
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asm::wfe();
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}
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}
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@ -0,0 +1,40 @@
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use core::sync::atomic::{compiler_fence, Ordering};
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use cortex_a::{barrier, regs::*};
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/// We assume that addr is cacheline aligned
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pub fn batch_modify(addr: u64) -> u32 {
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const CACHELINE_SIZE_BYTES: u64 = 64; // TODO: retrieve this from a system register
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const NUM_CACHELINES_TOUCHED: u64 = 5;
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const BYTES_PER_U64_REG: usize = 8;
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const NUM_BENCH_ITERATIONS: u64 = 100_000;
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const NUM_BYTES_TOUCHED: u64 = CACHELINE_SIZE_BYTES * NUM_CACHELINES_TOUCHED;
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let t1 = CNTPCT_EL0.get();
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compiler_fence(Ordering::SeqCst);
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let mut data_ptr: *mut u64;
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let mut temp: u64;
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for _ in 0..NUM_BENCH_ITERATIONS {
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for i in (addr..(addr + NUM_BYTES_TOUCHED)).step_by(BYTES_PER_U64_REG) {
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data_ptr = i as *mut u64;
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unsafe {
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temp = core::ptr::read_volatile(data_ptr);
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core::ptr::write_volatile(data_ptr, temp + 1);
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}
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}
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}
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// Insert a barrier to ensure that the last memory operation has finished
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// before we retrieve the elapsed time with the subsequent counter read. Not
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// needed at all given the sample size, but let's be a bit pedantic here for
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// education purposes. For measuring single-instructions, this would be
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// needed.
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unsafe { barrier::dsb(barrier::SY) };
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let t2 = CNTPCT_EL0.get();
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((t2 - t1) * 1000 / u64::from(CNTFRQ_EL0.get())) as u32
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}
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@ -0,0 +1,75 @@
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/*
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* MIT License
|
||||
*
|
||||
* Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
|
||||
use super::MMIO_BASE;
|
||||
use register::mmio::ReadWrite;
|
||||
|
||||
// Descriptions taken from
|
||||
// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
|
||||
register_bitfields! {
|
||||
u32,
|
||||
|
||||
/// GPIO Function Select 1
|
||||
GPFSEL1 [
|
||||
/// Pin 15
|
||||
FSEL15 OFFSET(15) NUMBITS(3) [
|
||||
Input = 0b000,
|
||||
Output = 0b001,
|
||||
RXD0 = 0b100, // UART0 - Alternate function 0
|
||||
RXD1 = 0b010 // Mini UART - Alternate function 5
|
||||
|
||||
],
|
||||
|
||||
/// Pin 14
|
||||
FSEL14 OFFSET(12) NUMBITS(3) [
|
||||
Input = 0b000,
|
||||
Output = 0b001,
|
||||
TXD0 = 0b100, // UART0 - Alternate function 0
|
||||
TXD1 = 0b010 // Mini UART - Alternate function 5
|
||||
]
|
||||
],
|
||||
|
||||
/// GPIO Pull-up/down Clock Register 0
|
||||
GPPUDCLK0 [
|
||||
/// Pin 15
|
||||
PUDCLK15 OFFSET(15) NUMBITS(1) [
|
||||
NoEffect = 0,
|
||||
AssertClock = 1
|
||||
],
|
||||
|
||||
/// Pin 14
|
||||
PUDCLK14 OFFSET(14) NUMBITS(1) [
|
||||
NoEffect = 0,
|
||||
AssertClock = 1
|
||||
]
|
||||
]
|
||||
}
|
||||
|
||||
pub const GPFSEL1: *const ReadWrite<u32, GPFSEL1::Register> =
|
||||
(MMIO_BASE + 0x0020_0004) as *const ReadWrite<u32, GPFSEL1::Register>;
|
||||
|
||||
pub const GPPUD: *const ReadWrite<u32> = (MMIO_BASE + 0x0020_0094) as *const ReadWrite<u32>;
|
||||
|
||||
pub const GPPUDCLK0: *const ReadWrite<u32, GPPUDCLK0::Register> =
|
||||
(MMIO_BASE + 0x0020_0098) as *const ReadWrite<u32, GPPUDCLK0::Register>;
|
||||
@ -0,0 +1,111 @@
|
||||
/*
|
||||
* MIT License
|
||||
*
|
||||
* Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(asm)]
|
||||
#![feature(const_fn)]
|
||||
|
||||
extern crate cortex_a;
|
||||
|
||||
#[macro_use]
|
||||
extern crate raspi3_boot;
|
||||
|
||||
#[macro_use]
|
||||
extern crate register;
|
||||
|
||||
const MMIO_BASE: u32 = 0x3F00_0000;
|
||||
|
||||
mod gpio;
|
||||
mod mbox;
|
||||
mod mmu;
|
||||
mod uart;
|
||||
mod benchmark;
|
||||
|
||||
fn do_benchmarks(uart: &uart::Uart) {
|
||||
const SIZE_2MIB: u64 = 2 * 1024 * 1024;
|
||||
|
||||
// Start of the __SECOND__ virtual 2 MiB block (counting starts at zero).
|
||||
// NON-cacheable DRAM memory.
|
||||
let non_cacheable_addr: u64 = SIZE_2MIB;
|
||||
|
||||
// Start of the __THIRD__ virtual 2 MiB block.
|
||||
// Cacheable DRAM memory
|
||||
let cacheable_addr: u64 = 2 * SIZE_2MIB;
|
||||
|
||||
uart.puts("Benchmarking non-cacheable DRAM modifications at virtual 0x");
|
||||
uart.hex(non_cacheable_addr as u32);
|
||||
uart.puts(", physical 0x");
|
||||
uart.hex(2 * SIZE_2MIB as u32);
|
||||
uart.puts(":\n");
|
||||
|
||||
let result_nc = benchmark::batch_modify(non_cacheable_addr);
|
||||
uart.dec(result_nc);
|
||||
uart.puts(" miliseconds.\n\n");
|
||||
|
||||
uart.puts("Benchmarking cacheable DRAM modifications at virtual 0x");
|
||||
uart.hex(cacheable_addr as u32);
|
||||
uart.puts(", physical 0x");
|
||||
uart.hex(2 * SIZE_2MIB as u32);
|
||||
uart.puts(":\n");
|
||||
let result_c = benchmark::batch_modify(cacheable_addr);
|
||||
uart.dec(result_c);
|
||||
uart.puts(" miliseconds.\n\n");
|
||||
|
||||
let percent_diff = (result_nc - result_c) * 100 / result_c;
|
||||
|
||||
uart.puts("With caching, the function is ");
|
||||
uart.dec(percent_diff);
|
||||
uart.puts("% faster!\n");
|
||||
}
|
||||
|
||||
entry!(kernel_entry);
|
||||
|
||||
fn kernel_entry() -> ! {
|
||||
let mut mbox = mbox::Mbox::new();
|
||||
let uart = uart::Uart::new(uart::UART_PHYS_BASE);
|
||||
|
||||
// set up serial console
|
||||
if uart.init(&mut mbox).is_err() {
|
||||
loop {
|
||||
cortex_a::asm::wfe() // If UART fails, abort early
|
||||
}
|
||||
}
|
||||
|
||||
uart.getc(); // Press a key first before being greeted
|
||||
uart.puts("Hello Rustacean!\n\n");
|
||||
|
||||
uart.puts("\nSwitching MMU on now...");
|
||||
|
||||
unsafe { mmu::init() };
|
||||
|
||||
uart.puts("MMU is live \\o/\n\n");
|
||||
|
||||
do_benchmarks(&uart);
|
||||
|
||||
// echo everything back
|
||||
loop {
|
||||
uart.send(uart.getc());
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,159 @@
|
||||
/*
|
||||
* MIT License
|
||||
*
|
||||
* Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
|
||||
use super::MMIO_BASE;
|
||||
use core::ops;
|
||||
use cortex_a::asm;
|
||||
use register::mmio::{ReadOnly, WriteOnly};
|
||||
|
||||
register_bitfields! {
|
||||
u32,
|
||||
|
||||
STATUS [
|
||||
FULL OFFSET(31) NUMBITS(1) [],
|
||||
EMPTY OFFSET(30) NUMBITS(1) []
|
||||
]
|
||||
}
|
||||
|
||||
const VIDEOCORE_MBOX: u32 = MMIO_BASE + 0xB880;
|
||||
|
||||
#[allow(non_snake_case)]
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
READ: ReadOnly<u32>, // 0x00
|
||||
__reserved_0: [u32; 5], // 0x04
|
||||
STATUS: ReadOnly<u32, STATUS::Register>, // 0x18
|
||||
__reserved_1: u32, // 0x1C
|
||||
WRITE: WriteOnly<u32>, // 0x20
|
||||
}
|
||||
|
||||
// Custom errors
|
||||
pub enum MboxError {
|
||||
ResponseError,
|
||||
UnknownError,
|
||||
}
|
||||
pub type Result<T> = ::core::result::Result<T, MboxError>;
|
||||
|
||||
// Channels
|
||||
pub mod channel {
|
||||
pub const PROP: u32 = 8;
|
||||
}
|
||||
|
||||
// Tags
|
||||
pub mod tag {
|
||||
pub const SETCLKRATE: u32 = 0x38002;
|
||||
pub const LAST: u32 = 0;
|
||||
}
|
||||
|
||||
// Clocks
|
||||
pub mod clock {
|
||||
pub const UART: u32 = 0x0_0000_0002;
|
||||
}
|
||||
|
||||
// Responses
|
||||
mod response {
|
||||
pub const SUCCESS: u32 = 0x8000_0000;
|
||||
pub const ERROR: u32 = 0x8000_0001; // error parsing request buffer (partial response)
|
||||
}
|
||||
|
||||
pub const REQUEST: u32 = 0;
|
||||
|
||||
// Public interface to the mailbox
|
||||
#[repr(C)]
|
||||
#[repr(align(16))]
|
||||
pub struct Mbox {
|
||||
// The address for buffer needs to be 16-byte aligned so that the
|
||||
// Videcore can handle it properly.
|
||||
pub buffer: [u32; 36],
|
||||
}
|
||||
|
||||
/// Deref to RegisterBlock
|
||||
///
|
||||
/// Allows writing
|
||||
/// ```
|
||||
/// self.STATUS.read()
|
||||
/// ```
|
||||
/// instead of something along the lines of
|
||||
/// ```
|
||||
/// unsafe { (*Mbox::ptr()).STATUS.read() }
|
||||
/// ```
|
||||
impl ops::Deref for Mbox {
|
||||
type Target = RegisterBlock;
|
||||
|
||||
fn deref(&self) -> &Self::Target {
|
||||
unsafe { &*Self::ptr() }
|
||||
}
|
||||
}
|
||||
|
||||
impl Mbox {
|
||||
pub fn new() -> Mbox {
|
||||
Mbox { buffer: [0; 36] }
|
||||
}
|
||||
|
||||
/// Returns a pointer to the register block
|
||||
fn ptr() -> *const RegisterBlock {
|
||||
VIDEOCORE_MBOX as *const _
|
||||
}
|
||||
|
||||
/// Make a mailbox call. Returns Err(MboxError) on failure, Ok(()) success
|
||||
pub fn call(&self, channel: u32) -> Result<()> {
|
||||
// wait until we can write to the mailbox
|
||||
loop {
|
||||
if !self.STATUS.is_set(STATUS::FULL) {
|
||||
break;
|
||||
}
|
||||
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
let buf_ptr = self.buffer.as_ptr() as u32;
|
||||
|
||||
// write the address of our message to the mailbox with channel identifier
|
||||
self.WRITE.set((buf_ptr & !0xF) | (channel & 0xF));
|
||||
|
||||
// now wait for the response
|
||||
loop {
|
||||
// is there a response?
|
||||
loop {
|
||||
if !self.STATUS.is_set(STATUS::EMPTY) {
|
||||
break;
|
||||
}
|
||||
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
let resp: u32 = self.READ.get();
|
||||
|
||||
// is it a response to our message?
|
||||
if ((resp & 0xF) == channel) && ((resp & !0xF) == buf_ptr) {
|
||||
// is it a valid successful response?
|
||||
return match self.buffer[1] {
|
||||
response::SUCCESS => Ok(()),
|
||||
response::ERROR => Err(MboxError::ResponseError),
|
||||
_ => Err(MboxError::UnknownError),
|
||||
};
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,219 @@
|
||||
/*
|
||||
* MIT License
|
||||
*
|
||||
* Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
|
||||
use cortex_a::{barrier, regs::*};
|
||||
|
||||
register_bitfields! {u64,
|
||||
// AArch64 Reference Manual page 2150
|
||||
STAGE1_DESCRIPTOR [
|
||||
/// Execute-never
|
||||
XN OFFSET(54) NUMBITS(1) [
|
||||
False = 0,
|
||||
True = 1
|
||||
],
|
||||
|
||||
/// Various address fields, depending on use case
|
||||
LVL2_OUTPUT_ADDR_4KiB OFFSET(21) NUMBITS(27) [], // [47:21]
|
||||
NEXT_LVL_TABLE_ADDR_4KiB OFFSET(12) NUMBITS(36) [], // [47:12]
|
||||
|
||||
/// Access flag
|
||||
AF OFFSET(10) NUMBITS(1) [
|
||||
False = 0,
|
||||
True = 1
|
||||
],
|
||||
|
||||
/// Shareability field
|
||||
SH OFFSET(8) NUMBITS(2) [
|
||||
OuterShareable = 0b10,
|
||||
InnerShareable = 0b11
|
||||
],
|
||||
|
||||
/// Access Permissions
|
||||
AP OFFSET(6) NUMBITS(2) [
|
||||
RW_EL1 = 0b00,
|
||||
RW_EL1_EL0 = 0b01,
|
||||
RO_EL1 = 0b10,
|
||||
RO_EL1_EL0 = 0b11
|
||||
],
|
||||
|
||||
/// Memory attributes index into the MAIR_EL1 register
|
||||
AttrIndx OFFSET(2) NUMBITS(3) [],
|
||||
|
||||
TYPE OFFSET(1) NUMBITS(1) [
|
||||
Block = 0,
|
||||
Table = 1
|
||||
],
|
||||
|
||||
VALID OFFSET(0) NUMBITS(1) [
|
||||
False = 0,
|
||||
True = 1
|
||||
]
|
||||
]
|
||||
}
|
||||
|
||||
trait BaseAddr {
|
||||
fn base_addr(&self) -> u64;
|
||||
}
|
||||
|
||||
impl BaseAddr for [u64; 512] {
|
||||
fn base_addr(&self) -> u64 {
|
||||
self as *const u64 as u64
|
||||
}
|
||||
}
|
||||
|
||||
const NUM_ENTRIES_4KIB: usize = 512;
|
||||
|
||||
static mut LVL2_TABLE: [u64; NUM_ENTRIES_4KIB] = [0; NUM_ENTRIES_4KIB];
|
||||
static mut SINGLE_LVL3_TABLE: [u64; NUM_ENTRIES_4KIB] = [0; NUM_ENTRIES_4KIB];
|
||||
|
||||
/// Set up identity mapped page tables for the first 1 gigabyte of address
|
||||
/// space.
|
||||
pub unsafe fn init() {
|
||||
// First, define the three memory types that we will map. Cacheable and
|
||||
// non-cacheable normal DRAM, and device.
|
||||
MAIR_EL1.write(
|
||||
// Attribute 2
|
||||
MAIR_EL1::Attr2_HIGH::Memory_OuterNonCacheable
|
||||
+ MAIR_EL1::Attr2_LOW_MEMORY::InnerNonCacheable
|
||||
|
||||
// Attribute 1
|
||||
+ MAIR_EL1::Attr1_HIGH::Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc
|
||||
+ MAIR_EL1::Attr1_LOW_MEMORY::InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc
|
||||
|
||||
// Attribute 0
|
||||
+ MAIR_EL1::Attr0_HIGH::Device
|
||||
+ MAIR_EL1::Attr0_LOW_DEVICE::Device_nGnRE,
|
||||
);
|
||||
|
||||
// Descriptive consts for indexing into the correct MAIR_EL1 attributes.
|
||||
mod mair {
|
||||
pub const DEVICE: u64 = 0;
|
||||
pub const NORMAL: u64 = 1;
|
||||
pub const NORMAL_NON_CACHEABLE: u64 = 2;
|
||||
}
|
||||
|
||||
// Set up the first LVL2 entry, pointing to a 4KiB table base address.
|
||||
let lvl3_base: u64 = SINGLE_LVL3_TABLE.base_addr() >> 12;
|
||||
LVL2_TABLE[0] = (STAGE1_DESCRIPTOR::VALID::True
|
||||
+ STAGE1_DESCRIPTOR::TYPE::Table
|
||||
+ STAGE1_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(lvl3_base))
|
||||
.value;
|
||||
|
||||
// The second 2 MiB block.
|
||||
LVL2_TABLE[1] = (STAGE1_DESCRIPTOR::VALID::True
|
||||
+ STAGE1_DESCRIPTOR::TYPE::Block
|
||||
+ STAGE1_DESCRIPTOR::AttrIndx.val(mair::NORMAL_NON_CACHEABLE)
|
||||
+ STAGE1_DESCRIPTOR::AP::RW_EL1
|
||||
+ STAGE1_DESCRIPTOR::SH::OuterShareable
|
||||
+ STAGE1_DESCRIPTOR::AF::True
|
||||
// This translation is accessed for virtual 0x200000. Point to physical
|
||||
// 0x400000, aka the third phyiscal 2 MiB DRAM block (third block == 2,
|
||||
// because we start counting at 0).
|
||||
//
|
||||
// Here, we configure it non-cacheable.
|
||||
+ STAGE1_DESCRIPTOR::LVL2_OUTPUT_ADDR_4KiB.val(2)
|
||||
+ STAGE1_DESCRIPTOR::XN::True)
|
||||
.value;
|
||||
|
||||
// Fill the rest of the LVL2 (2MiB) entries as block
|
||||
// descriptors. Differentiate between normal and device mem.
|
||||
let mmio_base: u64 = (super::MMIO_BASE >> 21).into();
|
||||
let common = STAGE1_DESCRIPTOR::VALID::True
|
||||
+ STAGE1_DESCRIPTOR::TYPE::Block
|
||||
+ STAGE1_DESCRIPTOR::AP::RW_EL1
|
||||
+ STAGE1_DESCRIPTOR::AF::True
|
||||
+ STAGE1_DESCRIPTOR::XN::True;
|
||||
|
||||
// Notice the skip(2). Start at the third 2 MiB DRAM block, which will point
|
||||
// virtual 0x400000 to physical 0x400000, configured as cacheable memory.
|
||||
for (i, entry) in LVL2_TABLE.iter_mut().enumerate().skip(2) {
|
||||
let j: u64 = i as u64;
|
||||
|
||||
let mem_attr = if j >= mmio_base {
|
||||
STAGE1_DESCRIPTOR::SH::OuterShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::DEVICE)
|
||||
} else {
|
||||
STAGE1_DESCRIPTOR::SH::InnerShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::NORMAL)
|
||||
};
|
||||
|
||||
*entry = (common + mem_attr + STAGE1_DESCRIPTOR::LVL2_OUTPUT_ADDR_4KiB.val(j)).value;
|
||||
}
|
||||
|
||||
// Finally, fill the single LVL3 table (4KiB granule). Differentiate between
|
||||
// code/RO and RW sections.
|
||||
//
|
||||
// Using the linker script, we ensure that the RO sections are 4KiB aligned,
|
||||
// and we export their boundaries via symbols.
|
||||
extern "C" {
|
||||
static mut __ro_start: u64;
|
||||
static mut __ro_end: u64;
|
||||
}
|
||||
|
||||
const PAGESIZE: u64 = 4096;
|
||||
let ro_start: u64 = &__ro_start as *const _ as u64 / PAGESIZE;
|
||||
let ro_end: u64 = &__ro_end as *const _ as u64 / PAGESIZE;
|
||||
let common = STAGE1_DESCRIPTOR::VALID::True
|
||||
+ STAGE1_DESCRIPTOR::TYPE::Table
|
||||
+ STAGE1_DESCRIPTOR::AttrIndx.val(mair::NORMAL)
|
||||
+ STAGE1_DESCRIPTOR::SH::InnerShareable
|
||||
+ STAGE1_DESCRIPTOR::AF::True;
|
||||
|
||||
for (i, entry) in SINGLE_LVL3_TABLE.iter_mut().enumerate() {
|
||||
let j: u64 = i as u64;
|
||||
|
||||
let mem_attr = if j < ro_start || j > ro_end {
|
||||
STAGE1_DESCRIPTOR::AP::RW_EL1 + STAGE1_DESCRIPTOR::XN::True
|
||||
} else {
|
||||
STAGE1_DESCRIPTOR::AP::RO_EL1 + STAGE1_DESCRIPTOR::XN::False
|
||||
};
|
||||
|
||||
*entry = (common + mem_attr + STAGE1_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(j)).value;
|
||||
}
|
||||
|
||||
// Point to the LVL2 table base address in TTBR0.
|
||||
TTBR0_EL1.set_baddr(LVL2_TABLE.base_addr());
|
||||
|
||||
// Configure various settings of stage 1 of the EL1 translation regime.
|
||||
let ips = ID_AA64MMFR0_EL1.read(ID_AA64MMFR0_EL1::PARange);
|
||||
TCR_EL1.write(
|
||||
TCR_EL1::TBI0::Ignored
|
||||
+ TCR_EL1::IPS.val(ips)
|
||||
+ TCR_EL1::TG0::KiB_4 // 4 KiB granule
|
||||
+ TCR_EL1::SH0::Inner
|
||||
+ TCR_EL1::ORGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable
|
||||
+ TCR_EL1::IRGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable
|
||||
+ TCR_EL1::EPD0::EnableTTBR0Walks
|
||||
+ TCR_EL1::T0SZ.val(34), // Start walks at level 2
|
||||
);
|
||||
|
||||
// Switch the MMU on.
|
||||
//
|
||||
// First, force all previous changes to be seen before the MMU is enabled.
|
||||
barrier::isb(barrier::SY);
|
||||
|
||||
// Enable the MMU and turn on caching
|
||||
SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable);
|
||||
|
||||
// Force MMU init to complete before next instruction
|
||||
barrier::isb(barrier::SY);
|
||||
}
|
||||
@ -0,0 +1,310 @@
|
||||
/*
|
||||
* MIT License
|
||||
*
|
||||
* Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
|
||||
use super::MMIO_BASE;
|
||||
use core::{
|
||||
ops,
|
||||
sync::atomic::{compiler_fence, Ordering},
|
||||
};
|
||||
use cortex_a::asm;
|
||||
use gpio;
|
||||
use mbox;
|
||||
use register::mmio::*;
|
||||
|
||||
// PL011 UART registers.
|
||||
//
|
||||
// Descriptions taken from
|
||||
// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
|
||||
register_bitfields! {
|
||||
u32,
|
||||
|
||||
/// Flag Register
|
||||
FR [
|
||||
/// Transmit FIFO full. The meaning of this bit depends on the
|
||||
/// state of the FEN bit in the UARTLCR_ LCRH Register. If the
|
||||
/// FIFO is disabled, this bit is set when the transmit
|
||||
/// holding register is full. If the FIFO is enabled, the TXFF
|
||||
/// bit is set when the transmit FIFO is full.
|
||||
TXFF OFFSET(5) NUMBITS(1) [],
|
||||
|
||||
/// Receive FIFO empty. The meaning of this bit depends on the
|
||||
/// state of the FEN bit in the UARTLCR_H Register. If the
|
||||
/// FIFO is disabled, this bit is set when the receive holding
|
||||
/// register is empty. If the FIFO is enabled, the RXFE bit is
|
||||
/// set when the receive FIFO is empty.
|
||||
RXFE OFFSET(4) NUMBITS(1) []
|
||||
],
|
||||
|
||||
/// Integer Baud rate divisor
|
||||
IBRD [
|
||||
/// Integer Baud rate divisor
|
||||
IBRD OFFSET(0) NUMBITS(16) []
|
||||
],
|
||||
|
||||
/// Fractional Baud rate divisor
|
||||
FBRD [
|
||||
/// Fractional Baud rate divisor
|
||||
FBRD OFFSET(0) NUMBITS(6) []
|
||||
],
|
||||
|
||||
/// Line Control register
|
||||
LCRH [
|
||||
/// Word length. These bits indicate the number of data bits
|
||||
/// transmitted or received in a frame.
|
||||
WLEN OFFSET(5) NUMBITS(2) [
|
||||
FiveBit = 0b00,
|
||||
SixBit = 0b01,
|
||||
SevenBit = 0b10,
|
||||
EightBit = 0b11
|
||||
]
|
||||
],
|
||||
|
||||
/// Control Register
|
||||
CR [
|
||||
/// Receive enable. If this bit is set to 1, the receive
|
||||
/// section of the UART is enabled. Data reception occurs for
|
||||
/// UART signals. When the UART is disabled in the middle of
|
||||
/// reception, it completes the current character before
|
||||
/// stopping.
|
||||
RXE OFFSET(9) NUMBITS(1) [
|
||||
Disabled = 0,
|
||||
Enabled = 1
|
||||
],
|
||||
|
||||
/// Transmit enable. If this bit is set to 1, the transmit
|
||||
/// section of the UART is enabled. Data transmission occurs
|
||||
/// for UART signals. When the UART is disabled in the middle
|
||||
/// of transmission, it completes the current character before
|
||||
/// stopping.
|
||||
TXE OFFSET(8) NUMBITS(1) [
|
||||
Disabled = 0,
|
||||
Enabled = 1
|
||||
],
|
||||
|
||||
/// UART enable
|
||||
UARTEN OFFSET(0) NUMBITS(1) [
|
||||
/// If the UART is disabled in the middle of transmission
|
||||
/// or reception, it completes the current character
|
||||
/// before stopping.
|
||||
Disabled = 0,
|
||||
Enabled = 1
|
||||
]
|
||||
],
|
||||
|
||||
/// Interupt Clear Register
|
||||
ICR [
|
||||
/// Meta field for all pending interrupts
|
||||
ALL OFFSET(0) NUMBITS(11) []
|
||||
]
|
||||
}
|
||||
|
||||
pub const UART_PHYS_BASE: u32 = MMIO_BASE + 0x20_1000;
|
||||
|
||||
#[allow(non_snake_case)]
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
DR: ReadWrite<u32>, // 0x00
|
||||
__reserved_0: [u32; 5], // 0x04
|
||||
FR: ReadOnly<u32, FR::Register>, // 0x18
|
||||
__reserved_1: [u32; 2], // 0x1c
|
||||
IBRD: WriteOnly<u32, IBRD::Register>, // 0x24
|
||||
FBRD: WriteOnly<u32, FBRD::Register>, // 0x28
|
||||
LCRH: WriteOnly<u32, LCRH::Register>, // 0x2C
|
||||
CR: WriteOnly<u32, CR::Register>, // 0x30
|
||||
__reserved_2: [u32; 4], // 0x34
|
||||
ICR: WriteOnly<u32, ICR::Register>, // 0x44
|
||||
}
|
||||
|
||||
pub enum UartError {
|
||||
MailboxError,
|
||||
}
|
||||
pub type Result<T> = ::core::result::Result<T, UartError>;
|
||||
|
||||
pub struct Uart {
|
||||
uart_base: u32,
|
||||
}
|
||||
|
||||
impl ops::Deref for Uart {
|
||||
type Target = RegisterBlock;
|
||||
|
||||
fn deref(&self) -> &Self::Target {
|
||||
unsafe { &*self.ptr() }
|
||||
}
|
||||
}
|
||||
|
||||
impl Uart {
|
||||
pub fn new(uart_base: u32) -> Uart {
|
||||
Uart { uart_base }
|
||||
}
|
||||
|
||||
/// Returns a pointer to the register block
|
||||
fn ptr(&self) -> *const RegisterBlock {
|
||||
self.uart_base as *const _
|
||||
}
|
||||
|
||||
///Set baud rate and characteristics (115200 8N1) and map to GPIO
|
||||
pub fn init(&self, mbox: &mut mbox::Mbox) -> Result<()> {
|
||||
// turn off UART0
|
||||
self.CR.set(0);
|
||||
|
||||
// set up clock for consistent divisor values
|
||||
mbox.buffer[0] = 9 * 4;
|
||||
mbox.buffer[1] = mbox::REQUEST;
|
||||
mbox.buffer[2] = mbox::tag::SETCLKRATE;
|
||||
mbox.buffer[3] = 12;
|
||||
mbox.buffer[4] = 8;
|
||||
mbox.buffer[5] = mbox::clock::UART; // UART clock
|
||||
mbox.buffer[6] = 4_000_000; // 4Mhz
|
||||
mbox.buffer[7] = 0; // skip turbo setting
|
||||
mbox.buffer[8] = mbox::tag::LAST;
|
||||
|
||||
// Insert a compiler fence that ensures that all stores to the
|
||||
// mbox buffer are finished before the GPU is signaled (which
|
||||
// is done by a store operation as well).
|
||||
compiler_fence(Ordering::Release);
|
||||
|
||||
if mbox.call(mbox::channel::PROP).is_err() {
|
||||
return Err(UartError::MailboxError); // Abort if UART clocks couldn't be set
|
||||
};
|
||||
|
||||
// map UART0 to GPIO pins
|
||||
unsafe {
|
||||
(*gpio::GPFSEL1).modify(gpio::GPFSEL1::FSEL14::TXD0 + gpio::GPFSEL1::FSEL15::RXD0);
|
||||
|
||||
(*gpio::GPPUD).set(0); // enable pins 14 and 15
|
||||
for _ in 0..150 {
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
(*gpio::GPPUDCLK0).modify(
|
||||
gpio::GPPUDCLK0::PUDCLK14::AssertClock + gpio::GPPUDCLK0::PUDCLK15::AssertClock,
|
||||
);
|
||||
for _ in 0..150 {
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
(*gpio::GPPUDCLK0).set(0);
|
||||
}
|
||||
|
||||
self.ICR.write(ICR::ALL::CLEAR);
|
||||
self.IBRD.write(IBRD::IBRD.val(2)); // Results in 115200 baud
|
||||
self.FBRD.write(FBRD::FBRD.val(0xB));
|
||||
self.LCRH.write(LCRH::WLEN::EightBit); // 8N1
|
||||
self.CR
|
||||
.write(CR::UARTEN::Enabled + CR::TXE::Enabled + CR::RXE::Enabled);
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Send a character
|
||||
pub fn send(&self, c: char) {
|
||||
// wait until we can send
|
||||
loop {
|
||||
if !self.FR.is_set(FR::TXFF) {
|
||||
break;
|
||||
}
|
||||
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
// write the character to the buffer
|
||||
self.DR.set(c as u32);
|
||||
}
|
||||
|
||||
/// Receive a character
|
||||
pub fn getc(&self) -> char {
|
||||
// wait until something is in the buffer
|
||||
loop {
|
||||
if !self.FR.is_set(FR::RXFE) {
|
||||
break;
|
||||
}
|
||||
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
// read it and return
|
||||
let mut ret = self.DR.get() as u8 as char;
|
||||
|
||||
// convert carrige return to newline
|
||||
if ret == '\r' {
|
||||
ret = '\n'
|
||||
}
|
||||
|
||||
ret
|
||||
}
|
||||
|
||||
/// Display a string
|
||||
pub fn puts(&self, string: &str) {
|
||||
for c in string.chars() {
|
||||
// convert newline to carrige return + newline
|
||||
if c == '\n' {
|
||||
self.send('\r')
|
||||
}
|
||||
|
||||
self.send(c);
|
||||
}
|
||||
}
|
||||
|
||||
/// Display a binary value in hexadecimal
|
||||
pub fn hex(&self, d: u32) {
|
||||
let mut n;
|
||||
|
||||
for i in 0..8 {
|
||||
// get highest tetrad
|
||||
n = d.wrapping_shr(28 - i * 4) & 0xF;
|
||||
|
||||
// 0-9 => '0'-'9', 10-15 => 'A'-'F'
|
||||
// Add proper offset for ASCII table
|
||||
if n > 9 {
|
||||
n += 0x37;
|
||||
} else {
|
||||
n += 0x30;
|
||||
}
|
||||
|
||||
self.send(n as u8 as char);
|
||||
}
|
||||
}
|
||||
|
||||
/// Display a binary value in decimal
|
||||
pub fn dec(&self, d: u32) {
|
||||
let mut digits: [char; 10] = ['\0'; 10];
|
||||
let mut d = d;
|
||||
let mut i: usize = 0;
|
||||
|
||||
loop {
|
||||
digits[i] = ((d % 10) + 0x30) as u8 as char;
|
||||
|
||||
i += 1;
|
||||
d /= 10;
|
||||
|
||||
if d == 0 {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for c in digits.iter().rev() {
|
||||
self.send(*c);
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue