01_wait_forever: support riscv64

01_wait_forever/Cargo.toml

@@ -10,5 +10,6 @@ default = []
 bsp_rpi3 = []
 bsp_rpi4 = []
 bsp_hifive1 = []
+bsp_hifive_unleashed = []
 
 [dependencies]

01_wait_forever/Makefile

@@ -37,6 +37,17 @@ else ifeq ($(BSP),hifive1)
     CPU_ARCH          = riscv32
     # Use its own image until rustembedded/osdev-utils supports riscv32.
     DOCKER_IMAGE      = imsuten/osdev-utils
+else ifeq ($(BSP),hifive_unleashed)
+    TARGET            = riscv64gc-unknown-none-elf
+    KERNEL_BIN        = kernel8.img
+    QEMU_BINARY       = qemu-system-riscv64
+    QEMU_MACHINE_TYPE = sifive_u
+    QEMU_RELEASE_ARGS = -d in_asm -display none -bios none
+    LINKER_FILE       = src/bsp/hifive_unleashed/link.ld
+    RUSTC_MISC_ARGS   = -C target-cpu=generic-rv64
+    CPU_ARCH          = riscv64
+    # Use its own image until rustembedded/osdev-utils supports riscv32.
+    DOCKER_IMAGE      = imsuten/osdev-utils
 endif
 
 # Export for build.rs
@@ -85,6 +96,9 @@ else ifeq ($(BSP),rpi4)
 qemu:
 	@echo "This board is not yet supported for QEMU."
 else ifeq ($(BSP),hifive1)
+qemu: $(KERNEL_ELF)
+	@$(DOCKER_QEMU) $(EXEC_QEMU) $(QEMU_RELEASE_ARGS) -kernel $(KERNEL_ELF)
+else ifeq ($(BSP),hifive_unleashed)
 qemu: $(KERNEL_ELF)
 	@$(DOCKER_QEMU) $(EXEC_QEMU) $(QEMU_RELEASE_ARGS) -kernel $(KERNEL_ELF)
 endif

01_wait_forever/src/_arch/riscv64/cpu.S

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0
+//
+// Copyright (c) 2020 Ken Kawamoto <kentaro.kawamoto@gmail.com>
+
+.section ".text._start"
+
+.global _start
+
+_start:
+1:  wfi         // Wait for interrupt
+    j       1b  // In case an event happened, jump back to 1

01_wait_forever/src/_arch/riscv64/cpu.rs

@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0
+//
+// Copyright (c) 2020 Ken Kawamoto <kentaro.kawamoto@gmail.com>
+
+//! Architectural processor code.
+
+// Assembly counterpart to this file.
+global_asm!(include_str!("cpu.S"));
+
+//--------------------------------------------------------------------------------------------------
+// Public Code
+//--------------------------------------------------------------------------------------------------
+
+/// Pause execution on the core.
+#[inline(always)]
+pub fn wait_forever() -> ! {
+    unsafe {
+        loop {
+            llvm_asm!("wfi"
+                    :             // outputs
+                    :             // inputs
+                    :             // clobbers
+                    : "volatile") // options
+        }
+    }
+}

01_wait_forever/src/bsp.rs

@@ -15,3 +15,9 @@ mod hifive1;
 
 #[cfg(feature = "bsp_hifive1")]
 pub use hifive1::*;
+
+#[cfg(feature = "bsp_hifive_unleashed")]
+mod hifive_unleashed;
+
+#[cfg(feature = "bsp_hifive_unleashed")]
+pub use hifive_unleashed::*;

01_wait_forever/src/bsp/hifive_unleashed.rs

@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0
+//
+// Copyright (c) 2020 Ken Kawamoto <kentaro.kawamoto@gmail.com>
+
+//! Top-level BSP file for the HiFive1.
+
+// Coming soon.

01_wait_forever/src/bsp/hifive_unleashed/link.ld

@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT OR Apache-2.0
+ *
+ * Copyright (c) 2020 Ken Kawamoto <kentaro.kawamoto@gmail.com>
+ */
+
+OUTPUT_ARCH("riscv")
+
+ENTRY(_start)
+
+SECTIONS
+{
+    /* Set current address to the value from which the HiFive1 starts execution */
+    . = 0x80000000;
+
+    .text :
+    {
+        *(.text._start) *(.text*)
+    }
+
+    /DISCARD/ : { *(.comment*) }
+}

01_wait_forever/src/cpu.rs

@@ -12,4 +12,8 @@ mod arch_cpu;
 #[path = "_arch/riscv32/cpu.rs"]
 mod arch_cpu;
 
+#[cfg(target_arch = "riscv64")]
+#[path = "_arch/riscv64/cpu.rs"]
+mod arch_cpu;
+
 pub use arch_cpu::*;