diff --git a/0C_virtual_memory/README.md b/0C_virtual_memory/README.md index 2d713220..c06ef170 100644 --- a/0C_virtual_memory/README.md +++ b/0C_virtual_memory/README.md @@ -27,6 +27,13 @@ Hopefully, in a later tutorial, we will write or use (e.g. from the `cortex-a` crate) proper modules for page table handling, that, among others, cover topics such as using recursive mapping for maintenace. +## Adress translation with the 4 KiB LVL3 table + +The following block diagram shows address translation by example of the UART's +Control Register (CR). + +![4 KiB translation block diagram](../doc/page_tables_4KiB.png) + ## Zero-cost abstraction The MMU init code is a good example to see the great potential of Rust's diff --git a/doc/page_tables_4KiB.png b/doc/page_tables_4KiB.png new file mode 100644 index 00000000..a06e7929 Binary files /dev/null and b/doc/page_tables_4KiB.png differ diff --git a/doc/page_tables_4KiB.svg b/doc/page_tables_4KiB.svg new file mode 100644 index 00000000..4d61d43e --- /dev/null +++ b/doc/page_tables_4KiB.svg @@ -0,0 +1,1556 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + ... + 0 + 127 + Stack + Stack + + + + + ... + Code + RO data + Code + RO data + 128 + + + + + ... + Data and BSS + Data and BSS + + + + ... + Remapped UART + 511 + + + + 0 + + ... + Device MMIO + + + + ... + 511 + 504 + Device MMIO + + REMAPPED_UART_BASE + CR_Offset =0x001F_F000 + 0x30 = 0x001F_F030 =0b000000000_111111111_000000110000 + + TTBR_EL1 + + LVL2 tablebase address + LVL3 Table base addr + static mut LVL2_TABLE + static mut LVL3_TABLE + } + + Select entry 0 ofLVL2 table + + } + Virtual Address: + + 0b1_1111_1111 = 511Select entry 511 ofLVL3 table + + APAccessPermissions + 53 + 12 + 47 + 9 + 10 + 8 + 6 + 7 + 4 + 1 + 2 + 0 + + + MAIR_EL1index + + TYPE + VALID + + + + SHShareability + AFAccessFlag + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PXNPrivilegedexecutenever + 63 + + + + + + Final 48 Bit Physical Address: 0x3F201030 + + + 0x3F201 + + 0x030 + + 0x3F201 + } + + + 0 + 11 + 47 + 12 + Entry contains baseaddress of follow-upLVL3 Table. + The LVL3 PT entry pointsto the start address ofa 4KiB frame. The last12 Bit of the VA are theindex into the frame. + output address + +