Fix correct term usec for microseconds

09_delays/README.md

@@ -10,10 +10,10 @@ other two are µs based.
 `delays::wait_cycles(cyc: u32)` this is very straightforward, we execute the
 `nop` instruction n times.
 
-`delays::wait_msec(n: u32)` this implementation uses ARM system registers
+`delays::wait_usec(n: u32)` this implementation uses ARM system registers
 (available on all AArch64 CPUs).
 
-`delays::SysTmr::wait_msec_st(&self, n: u64)` is a BCM specific implementation,
+`delays::SysTmr::wait_usec_st(&self, n: u64)` is a BCM specific implementation,
 which uses the System Timer peripheral (not available on qemu).
 
 ## uart.rs

09_delays/src/delays.rs

@@ -1,7 +1,7 @@
 /*
  * MIT License
  *
- * Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
+ * Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -81,7 +81,7 @@ impl SysTmr {
     }
 
     /// Wait N microsec (with BCM System Timer)
-    pub fn wait_msec_st(&self, n: u64) {
+    pub fn wait_usec_st(&self, n: u64) {
         let t = self.get_system_timer();
 
         // We must check if it's non-zero, because qemu does not
@@ -103,7 +103,7 @@ impl SysTmr {
  *
  */
 /// Wait N microsec (ARM CPU only)
-pub fn wait_msec(n: u32) {
+pub fn wait_usec(n: u32) {
     // Get the counter frequency
     let frq = CNTFRQ_EL0.get();
 

09_delays/src/main.rs

@@ -1,7 +1,7 @@
 /*
  * MIT License
  *
- * Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
+ * Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -53,19 +53,19 @@ fn kernel_entry() -> ! {
     uart.puts("OK\n");
 
     uart.puts("[i] Waiting 1 second (ARM CPU): ");
-    delays::wait_msec(1_000_000);
+    delays::wait_usec(1_000_000);
     uart.puts("OK\n");
 
     let t = delays::SysTmr::new();
     if t.get_system_timer() != 0 {
         uart.puts("[i] Waiting 1 second (BCM System Timer): ");
-        t.wait_msec_st(1_000_000);
+        t.wait_usec_st(1_000_000);
         uart.puts("OK\n");
     }
 
     uart.puts("[i] Looping forever now!\n");
     loop {
-        delays::wait_msec(1_000_000);
+        delays::wait_usec(1_000_000);
         uart.puts("Tick: 1s\n");
     }
 }

0B_exception_levels/src/delays.rs

@@ -1,7 +1,7 @@
 /*
  * MIT License
  *
- * Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
+ * Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -31,7 +31,7 @@ use cortex_a::regs::*;
  *
  */
 /// Wait N microsec (ARM CPU only)
-pub fn wait_msec(n: u32) {
+pub fn wait_usec(n: u32) {
     // Get the counter frequency
     let frq = CNTFRQ_EL0.get();
 

0B_exception_levels/src/main.rs

@@ -1,7 +1,7 @@
 /*
  * MIT License
  *
- * Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
+ * Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -39,11 +39,11 @@ fn check_timer(uart: &uart::Uart) {
         "Testing EL1 access to timer registers:\
          \n    Delaying for 3 seconds now.\n",
     );
-    delays::wait_msec(1_000_000);
+    delays::wait_usec(1_000_000);
     uart.puts("    1..");
-    delays::wait_msec(1_000_000);
+    delays::wait_usec(1_000_000);
     uart.puts("2..");
-    delays::wait_msec(1_000_000);
+    delays::wait_usec(1_000_000);
     uart.puts(
         "3\
          \n    Works!\n\n",