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chore(bcm): update pl011_uart RXFF register

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pull/126/head
lightning1141 3 years ago
parent b1c438dc66
commit f7531d8bca
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GPG Key ID: 226B076640A284D6
14 changed files with 57 additions and 57 deletions
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10
05_drivers_gpio_uart/README.md
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@ -509,12 +509,12 @@ diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 05_dri
+ /// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
+ TXFF OFFSET(5) NUMBITS(1) [],
+
+ /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
+ /// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the
+ /// LCR_H Register.
+ ///
+ /// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
+ /// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
+
+ /// - If the FIFO is disabled, this bit is set when the receive holding register is full.
+ /// - If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
+ RXFF OFFSET(6) NUMBITS(1) [],
+ /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
+ /// LCR_H Register.
+ ///

8
05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -47,11 +47,11 @@ register_bitfields! {
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
TXFF OFFSET(5) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.
///
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
/// - If the FIFO is disabled, this bit is set when the receive holding register is full.
/// - If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
RXFF OFFSET(6) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.

8
06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -47,11 +47,11 @@ register_bitfields! {
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
TXFF OFFSET(5) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.
///
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
/// - If the FIFO is disabled, this bit is set when the receive holding register is full.
/// - If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
RXFF OFFSET(6) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.

8
07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -47,11 +47,11 @@ register_bitfields! {
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
TXFF OFFSET(5) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.
///
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
/// - If the FIFO is disabled, this bit is set when the receive holding register is full.
/// - If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
RXFF OFFSET(6) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.

8
08_hw_debug_JTAG/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -47,11 +47,11 @@ register_bitfields! {
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
TXFF OFFSET(5) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.
///
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
/// - If the FIFO is disabled, this bit is set when the receive holding register is full.
/// - If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
RXFF OFFSET(6) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.

8
09_privilege_level/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -47,11 +47,11 @@ register_bitfields! {
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
TXFF OFFSET(5) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.
///
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
/// - If the FIFO is disabled, this bit is set when the receive holding register is full.
/// - If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
RXFF OFFSET(6) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.

8
10_virtual_mem_part1_identity_mapping/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -47,11 +47,11 @@ register_bitfields! {
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
TXFF OFFSET(5) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.
///
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
/// - If the FIFO is disabled, this bit is set when the receive holding register is full.
/// - If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
RXFF OFFSET(6) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.

8
11_exceptions_part1_groundwork/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -47,11 +47,11 @@ register_bitfields! {
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
TXFF OFFSET(5) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.
///
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
/// - If the FIFO is disabled, this bit is set when the receive holding register is full.
/// - If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
RXFF OFFSET(6) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.

8
12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -47,11 +47,11 @@ register_bitfields! {
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
TXFF OFFSET(5) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.
///
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
/// - If the FIFO is disabled, this bit is set when the receive holding register is full.
/// - If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
RXFF OFFSET(6) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.

8
13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -47,11 +47,11 @@ register_bitfields! {
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
TXFF OFFSET(5) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.
///
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
/// - If the FIFO is disabled, this bit is set when the receive holding register is full.
/// - If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
RXFF OFFSET(6) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.

8
14_virtual_mem_part2_mmio_remap/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -50,11 +50,11 @@ register_bitfields! {
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
TXFF OFFSET(5) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.
///
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
/// - If the FIFO is disabled, this bit is set when the receive holding register is full.
/// - If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
RXFF OFFSET(6) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.

8
15_virtual_mem_part3_precomputed_tables/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -50,11 +50,11 @@ register_bitfields! {
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
TXFF OFFSET(5) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.
///
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
/// - If the FIFO is disabled, this bit is set when the receive holding register is full.
/// - If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
RXFF OFFSET(6) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.

8
16_virtual_mem_part4_higher_half_kernel/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -50,11 +50,11 @@ register_bitfields! {
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
TXFF OFFSET(5) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.
///
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
/// - If the FIFO is disabled, this bit is set when the receive holding register is full.
/// - If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
RXFF OFFSET(6) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.

8
X1_JTAG_boot/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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@ -47,11 +47,11 @@ register_bitfields! {
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
TXFF OFFSET(5) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.
///
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
/// - If the FIFO is disabled, this bit is set when the receive holding register is full.
/// - If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
RXFF OFFSET(6) NUMBITS(1) [],
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
/// LCR_H Register.

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