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147 lines
4.2 KiB
Rust
147 lines
4.2 KiB
Rust
// SPDX-License-Identifier: MIT OR Apache-2.0
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//
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// Copyright (c) 2020 Andre Richter <andre.o.richter@gmail.com>
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//! GICC Driver - GIC CPU interface.
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use crate::exception;
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use core::ops;
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use register::{mmio::*, register_bitfields, register_structs};
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//--------------------------------------------------------------------------------------------------
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// Private Definitions
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//--------------------------------------------------------------------------------------------------
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register_bitfields! {
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u32,
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/// CPU Interface Control Register
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CTLR [
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Enable OFFSET(0) NUMBITS(1) []
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],
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/// Interrupt Priority Mask Register
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PMR [
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Priority OFFSET(0) NUMBITS(8) []
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],
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/// Interrupt Acknowledge Register
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IAR [
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InterruptID OFFSET(0) NUMBITS(10) []
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],
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/// End of Interrupt Register
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EOIR [
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EOIINTID OFFSET(0) NUMBITS(10) []
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]
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}
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//--------------------------------------------------------------------------------------------------
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// Public Definitions
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//--------------------------------------------------------------------------------------------------
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register_structs! {
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#[allow(non_snake_case)]
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pub RegisterBlock {
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(0x000 => CTLR: ReadWrite<u32, CTLR::Register>),
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(0x004 => PMR: ReadWrite<u32, PMR::Register>),
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(0x008 => _reserved1),
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(0x00C => IAR: ReadWrite<u32, IAR::Register>),
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(0x010 => EOIR: ReadWrite<u32, EOIR::Register>),
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(0x014 => @END),
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}
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}
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/// Representation of the GIC CPU interface.
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pub struct GICC {
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base_addr: usize,
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}
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//--------------------------------------------------------------------------------------------------
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// Public Code
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//--------------------------------------------------------------------------------------------------
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impl ops::Deref for GICC {
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type Target = RegisterBlock;
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fn deref(&self) -> &Self::Target {
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unsafe { &*self.ptr() }
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}
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}
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impl GICC {
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/// Create an instance.
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///
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/// # Safety
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///
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/// - The user must ensure to provide the correct `base_addr`.
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pub const unsafe fn new(base_addr: usize) -> Self {
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Self { base_addr }
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}
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/// Return a pointer to the associated MMIO register block.
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fn ptr(&self) -> *const RegisterBlock {
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self.base_addr as *const _
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}
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/// Accept interrupts of any priority.
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///
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/// Quoting the GICv2 Architecture Specification:
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///
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/// "Writing 255 to the GICC_PMR always sets it to the largest supported priority field
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/// value."
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///
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/// # Safety
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///
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/// - GICC MMIO registers are banked per CPU core. It is therefore safe to have `&self` instead
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/// of `&mut self`.
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pub fn priority_accept_all(&self) {
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self.PMR.write(PMR::Priority.val(255)); // Comment in arch spec.
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}
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/// Enable the interface - start accepting IRQs.
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///
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/// # Safety
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///
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/// - GICC MMIO registers are banked per CPU core. It is therefore safe to have `&self` instead
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/// of `&mut self`.
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pub fn enable(&self) {
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self.CTLR.write(CTLR::Enable::SET);
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}
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/// Extract the number of the highest-priority pending IRQ.
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///
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/// Can only be called from IRQ context, which is ensured by taking an `IRQContext` token.
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///
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/// # Safety
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///
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/// - GICC MMIO registers are banked per CPU core. It is therefore safe to have `&self` instead
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/// of `&mut self`.
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#[allow(clippy::trivially_copy_pass_by_ref)]
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pub fn get_pending_number<'irq_context>(
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&self,
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_ic: &exception::asynchronous::IRQContext<'irq_context>,
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) -> usize {
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self.IAR.read(IAR::InterruptID) as usize
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}
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/// Complete handling of the currently active IRQ.
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///
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/// Can only be called from IRQ context, which is ensured by taking an `IRQContext` token.
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///
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/// To be called after `get_pending_number()`.
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///
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/// # Safety
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///
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/// - GICC MMIO registers are banked per CPU core. It is therefore safe to have `&self` instead
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/// of `&mut self`.
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#[allow(clippy::trivially_copy_pass_by_ref)]
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pub fn mark_comleted<'irq_context>(
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&self,
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irq_number: u32,
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_ic: &exception::asynchronous::IRQContext<'irq_context>,
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) {
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self.EOIR.write(EOIR::EOIINTID.val(irq_number));
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}
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}
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