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139 lines
3.9 KiB
Rust
139 lines
3.9 KiB
Rust
// SPDX-License-Identifier: MIT OR Apache-2.0
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//
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// Copyright (c) 2018-2020 Andre Richter <andre.o.richter@gmail.com>
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//! GPIO Driver.
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use crate::{
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bsp::device_driver::common::MMIODerefWrapper, cpu, driver, synchronization,
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synchronization::IRQSafeNullLock,
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};
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use register::{mmio::*, register_bitfields, register_structs};
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//--------------------------------------------------------------------------------------------------
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// Private Definitions
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//--------------------------------------------------------------------------------------------------
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// GPIO registers.
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//
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// Descriptions taken from
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// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
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register_bitfields! {
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u32,
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/// GPIO Function Select 1
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GPFSEL1 [
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/// Pin 15
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FSEL15 OFFSET(15) NUMBITS(3) [
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Input = 0b000,
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Output = 0b001,
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AltFunc0 = 0b100 // PL011 UART RX
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],
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/// Pin 14
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FSEL14 OFFSET(12) NUMBITS(3) [
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Input = 0b000,
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Output = 0b001,
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AltFunc0 = 0b100 // PL011 UART TX
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]
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],
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/// GPIO Pull-up/down Clock Register 0
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GPPUDCLK0 [
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/// Pin 15
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PUDCLK15 OFFSET(15) NUMBITS(1) [
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NoEffect = 0,
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AssertClock = 1
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],
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/// Pin 14
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PUDCLK14 OFFSET(14) NUMBITS(1) [
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NoEffect = 0,
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AssertClock = 1
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]
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]
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}
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register_structs! {
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#[allow(non_snake_case)]
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RegisterBlock {
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(0x00 => GPFSEL0: ReadWrite<u32>),
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(0x04 => GPFSEL1: ReadWrite<u32, GPFSEL1::Register>),
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(0x08 => GPFSEL2: ReadWrite<u32>),
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(0x0C => GPFSEL3: ReadWrite<u32>),
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(0x10 => GPFSEL4: ReadWrite<u32>),
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(0x14 => GPFSEL5: ReadWrite<u32>),
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(0x18 => _reserved1),
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(0x94 => GPPUD: ReadWrite<u32>),
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(0x98 => GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>),
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(0x9C => GPPUDCLK1: ReadWrite<u32>),
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(0xA0 => @END),
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}
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}
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/// Abstraction for the associated MMIO registers.
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type Regs = MMIODerefWrapper<RegisterBlock>;
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//--------------------------------------------------------------------------------------------------
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// Public Definitions
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//--------------------------------------------------------------------------------------------------
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/// Representation of the GPIO HW.
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pub struct GPIO {
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inner: IRQSafeNullLock<Regs>,
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}
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//--------------------------------------------------------------------------------------------------
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// Public Code
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//--------------------------------------------------------------------------------------------------
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impl GPIO {
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/// Create an instance.
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///
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/// # Safety
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///
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/// - The user must ensure to provide the correct `base_addr`.
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pub const unsafe fn new(base_addr: usize) -> Self {
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Self {
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inner: IRQSafeNullLock::new(Regs::new(base_addr)),
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}
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}
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/// Map PL011 UART as standard output.
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///
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/// TX to pin 14
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/// RX to pin 15
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pub fn map_pl011_uart(&self) {
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let mut r = &self.inner;
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r.lock(|inner| {
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// Map to pins.
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inner
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.GPFSEL1
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.modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0);
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// Enable pins 14 and 15.
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inner.GPPUD.set(0);
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cpu::spin_for_cycles(150);
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inner
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.GPPUDCLK0
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.write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
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cpu::spin_for_cycles(150);
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inner.GPPUDCLK0.set(0);
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})
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}
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}
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//------------------------------------------------------------------------------
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// OS Interface Code
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//------------------------------------------------------------------------------
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use synchronization::interface::Mutex;
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impl driver::interface::DeviceDriver for GPIO {
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fn compatible(&self) -> &str {
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"BCM GPIO"
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}
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}
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