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125 lines
4.4 KiB
Rust
125 lines
4.4 KiB
Rust
// SPDX-License-Identifier: MIT OR Apache-2.0
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//
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// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com>
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//! BSP Memory Management.
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pub mod mmu;
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use core::{cell::UnsafeCell, ops::RangeInclusive};
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//--------------------------------------------------------------------------------------------------
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// Private Definitions
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//--------------------------------------------------------------------------------------------------
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// Symbols from the linker script.
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extern "Rust" {
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static __rx_start: UnsafeCell<()>;
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static __rx_end_exclusive: UnsafeCell<()>;
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static __bss_start: UnsafeCell<u64>;
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static __bss_end_inclusive: UnsafeCell<u64>;
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}
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//--------------------------------------------------------------------------------------------------
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// Public Definitions
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//--------------------------------------------------------------------------------------------------
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/// The board's physical memory map.
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#[rustfmt::skip]
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pub(super) mod map {
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/// The inclusive end address of the memory map.
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///
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/// End address + 1 must be power of two.
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///
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/// # Note
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///
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/// RPi3 and RPi4 boards can have different amounts of RAM. To make our code lean for
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/// educational purposes, we set the max size of the address space to 4 GiB regardless of board.
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/// This way, we can map the entire range that we need (end of MMIO for RPi4) in one take.
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///
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/// However, making this trade-off has the downside of making it possible for the CPU to assert a
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/// physical address that is not backed by any DRAM (e.g. accessing an address close to 4 GiB on
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/// an RPi3 that comes with 1 GiB of RAM). This would result in a crash or other kind of error.
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pub const END_INCLUSIVE: usize = 0xFFFF_FFFF;
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pub const GPIO_OFFSET: usize = 0x0020_0000;
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pub const UART_OFFSET: usize = 0x0020_1000;
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/// Physical devices.
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#[cfg(feature = "bsp_rpi3")]
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pub mod mmio {
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use super::*;
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pub const START: usize = 0x3F00_0000;
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pub const PERIPHERAL_INTERRUPT_CONTROLLER_START: usize = START + 0x0000_B200;
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pub const GPIO_START: usize = START + GPIO_OFFSET;
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pub const PL011_UART_START: usize = START + UART_OFFSET;
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pub const LOCAL_INTERRUPT_CONTROLLER_START: usize = 0x4000_0000;
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pub const END_INCLUSIVE: usize = 0x4000_FFFF;
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}
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/// Physical devices.
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#[cfg(feature = "bsp_rpi4")]
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pub mod mmio {
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use super::*;
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pub const START: usize = 0xFE00_0000;
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pub const GPIO_START: usize = START + GPIO_OFFSET;
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pub const PL011_UART_START: usize = START + UART_OFFSET;
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pub const GICD_START: usize = 0xFF84_1000;
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pub const GICC_START: usize = 0xFF84_2000;
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pub const END_INCLUSIVE: usize = 0xFF84_FFFF;
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}
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}
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//--------------------------------------------------------------------------------------------------
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// Private Code
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//--------------------------------------------------------------------------------------------------
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/// Start address of the Read+Execute (RX) range.
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///
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/// # Safety
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///
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/// - Value is provided by the linker script and must be trusted as-is.
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#[inline(always)]
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fn rx_start() -> usize {
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unsafe { __rx_start.get() as usize }
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}
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/// Exclusive end address of the Read+Execute (RX) range.
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///
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/// # Safety
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///
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/// - Value is provided by the linker script and must be trusted as-is.
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#[inline(always)]
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fn rx_end_exclusive() -> usize {
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unsafe { __rx_end_exclusive.get() as usize }
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}
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//--------------------------------------------------------------------------------------------------
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// Public Code
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//--------------------------------------------------------------------------------------------------
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/// Exclusive end address of the boot core's stack.
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#[inline(always)]
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pub fn boot_core_stack_end() -> usize {
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rx_start()
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}
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/// Return the inclusive range spanning the .bss section.
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///
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/// # Safety
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///
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/// - Values are provided by the linker script and must be trusted as-is.
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/// - The linker-provided addresses must be u64 aligned.
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pub fn bss_range_inclusive() -> RangeInclusive<*mut u64> {
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let range;
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unsafe {
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range = RangeInclusive::new(__bss_start.get(), __bss_end_inclusive.get());
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}
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assert!(!range.is_empty());
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range
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}
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