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285 lines
8.6 KiB
Rust
285 lines
8.6 KiB
Rust
// SPDX-License-Identifier: MIT
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//
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// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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//! Exception handling.
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use core::fmt;
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use cortex_a::{asm, barrier, regs::*};
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use register::InMemoryRegister;
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// Assembly counterpart to this file.
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global_asm!(include_str!("exception.S"));
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/// Wrapper struct for memory copy of SPSR_EL1.
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#[repr(transparent)]
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struct SpsrEL1(InMemoryRegister<u32, SPSR_EL1::Register>);
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/// The exception context as it is stored on the stack on exception entry.
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#[repr(C)]
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struct ExceptionContext {
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// General Purpose Registers.
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gpr: [u64; 30],
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// The link register, aka x30.
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lr: u64,
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// Exception link register. The program counter at the time the exception happened.
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elr_el1: u64,
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// Saved program status.
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spsr_el1: SpsrEL1,
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}
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/// Wrapper struct for pretty printing ESR_EL1.
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struct EsrEL1;
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//--------------------------------------------------------------------------------------------------
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// Exception vector implementation
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//--------------------------------------------------------------------------------------------------
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/// Print verbose information about the exception and the panic.
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fn default_exception_handler(e: &ExceptionContext) {
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panic!(
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"\n\nCPU Exception!\n\
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FAR_EL1: {:#018x}\n\
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{}\n\
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{}",
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FAR_EL1.get(),
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EsrEL1 {},
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e
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);
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}
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//--------------------------------------------------------------------------------------------------
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// Current, EL0
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//--------------------------------------------------------------------------------------------------
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#[no_mangle]
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unsafe extern "C" fn current_el0_synchronous(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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#[no_mangle]
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unsafe extern "C" fn current_el0_irq(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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#[no_mangle]
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unsafe extern "C" fn current_el0_serror(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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//--------------------------------------------------------------------------------------------------
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// Current, ELx
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//--------------------------------------------------------------------------------------------------
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/// Asynchronous exception taken from the current EL, using SP of the current EL.
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#[no_mangle]
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unsafe extern "C" fn current_elx_synchronous(e: &mut ExceptionContext) {
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let far_el1 = FAR_EL1.get();
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// This catches the demo case for this tutorial. If the fault address happens to be 8 GiB,
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// advance the exception link register for one instruction, so that execution can continue.
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if far_el1 == 8 * 1024 * 1024 * 1024 {
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e.elr_el1 += 4;
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asm::eret()
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}
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default_exception_handler(e);
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}
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#[no_mangle]
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unsafe extern "C" fn current_elx_irq(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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#[no_mangle]
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unsafe extern "C" fn current_elx_serror(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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//--------------------------------------------------------------------------------------------------
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// Lower, AArch64
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//--------------------------------------------------------------------------------------------------
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#[no_mangle]
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unsafe extern "C" fn lower_aarch64_synchronous(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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#[no_mangle]
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unsafe extern "C" fn lower_aarch64_irq(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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#[no_mangle]
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unsafe extern "C" fn lower_aarch64_serror(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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//--------------------------------------------------------------------------------------------------
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// Lower, AArch32
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//--------------------------------------------------------------------------------------------------
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#[no_mangle]
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unsafe extern "C" fn lower_aarch32_synchronous(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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#[no_mangle]
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unsafe extern "C" fn lower_aarch32_irq(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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#[no_mangle]
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unsafe extern "C" fn lower_aarch32_serror(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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//--------------------------------------------------------------------------------------------------
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// Pretty printing
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//--------------------------------------------------------------------------------------------------
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/// Human readable ESR_EL1.
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#[rustfmt::skip]
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impl fmt::Display for EsrEL1 {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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let esr_el1 = ESR_EL1.extract();
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// Raw print of whole register.
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writeln!(f, "ESR_EL1: {:#010x}", esr_el1.get())?;
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// Raw print of exception class.
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write!(f, " Exception Class (EC) : {:#x}", esr_el1.read(ESR_EL1::EC))?;
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// Exception class, translation.
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let ec_translation = match esr_el1.read_as_enum(ESR_EL1::EC) {
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Some(ESR_EL1::EC::Value::DataAbortCurrentEL) => "Data Abort, current EL",
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_ => "N/A",
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};
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writeln!(f, " - {}", ec_translation)?;
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// Raw print of instruction specific syndrome.
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write!(f, " Instr Specific Syndrome (ISS): {:#x}", esr_el1.read(ESR_EL1::ISS))?;
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Ok(())
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}
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}
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/// Human readable SPSR_EL1.
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#[rustfmt::skip]
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impl fmt::Display for SpsrEL1 {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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// Raw value.
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writeln!(f, "SPSR_EL1: {:#010x}", self.0.get())?;
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let to_flag_str = |x| -> _ {
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if x { "Set" } else { "Not set" }
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};
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writeln!(f, " Flags:")?;
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writeln!(f, " Negative (N): {}", to_flag_str(self.0.is_set(SPSR_EL1::N)))?;
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writeln!(f, " Zero (Z): {}", to_flag_str(self.0.is_set(SPSR_EL1::Z)))?;
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writeln!(f, " Carry (C): {}", to_flag_str(self.0.is_set(SPSR_EL1::C)))?;
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writeln!(f, " Overflow (V): {}", to_flag_str(self.0.is_set(SPSR_EL1::V)))?;
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let to_mask_str = |x| -> _ {
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if x { "Masked" } else { "Unmasked" }
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};
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writeln!(f, " Exception handling state:")?;
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writeln!(f, " Debug (D): {}", to_mask_str(self.0.is_set(SPSR_EL1::D)))?;
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writeln!(f, " SError (A): {}", to_mask_str(self.0.is_set(SPSR_EL1::A)))?;
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writeln!(f, " IRQ (I): {}", to_mask_str(self.0.is_set(SPSR_EL1::I)))?;
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writeln!(f, " FIQ (F): {}", to_mask_str(self.0.is_set(SPSR_EL1::F)))?;
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write!(f, " Illegal Execution State (IL): {}",
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to_flag_str(self.0.is_set(SPSR_EL1::IL))
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)?;
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Ok(())
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}
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}
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/// Human readable print of the exception context.
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impl fmt::Display for ExceptionContext {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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writeln!(f, "ELR_EL1: {:#018x}", self.elr_el1)?;
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writeln!(f, "{}", self.spsr_el1)?;
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writeln!(f)?;
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writeln!(f, "General purpose register:")?;
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#[rustfmt::skip]
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let alternating = |x| -> _ {
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if x % 2 == 0 { " " } else { "\n" }
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};
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// Print two registers per line.
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for (i, reg) in self.gpr.iter().enumerate() {
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write!(f, " x{: <2}: {: >#018x}{}", i, reg, alternating(i))?;
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}
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write!(f, " lr : {:#018x}", self.lr)?;
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Ok(())
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}
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}
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//--------------------------------------------------------------------------------------------------
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// Arch-public
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//--------------------------------------------------------------------------------------------------
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/// Set the exception vector base address register.
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///
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/// # Safety
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///
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/// - The vector table and the symbol `__exception_vector_table_start` from the linker script must
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/// adhere to the alignment and size constraints demanded by the AArch64 spec.
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pub unsafe fn set_vbar_el1() {
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// Provided by exception.S.
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extern "C" {
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static mut __exception_vector_start: u64;
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}
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let addr: u64 = &__exception_vector_start as *const _ as u64;
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VBAR_EL1.set(addr);
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// Force VBAR update to complete before next instruction.
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barrier::isb(barrier::SY);
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}
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pub trait DaifField {
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fn daif_field() -> register::Field<u32, DAIF::Register>;
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}
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pub struct Debug;
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pub struct SError;
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pub struct IRQ;
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pub struct FIQ;
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impl DaifField for Debug {
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fn daif_field() -> register::Field<u32, DAIF::Register> {
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DAIF::D
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}
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}
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impl DaifField for SError {
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fn daif_field() -> register::Field<u32, DAIF::Register> {
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DAIF::A
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}
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}
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impl DaifField for IRQ {
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fn daif_field() -> register::Field<u32, DAIF::Register> {
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DAIF::I
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}
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}
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impl DaifField for FIQ {
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fn daif_field() -> register::Field<u32, DAIF::Register> {
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DAIF::F
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}
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}
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pub fn is_masked<T: DaifField>() -> bool {
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DAIF.is_set(T::daif_field())
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}
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