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178 lines
7.2 KiB
C
178 lines
7.2 KiB
C
/*
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* Copyright (C) 2018 bzt (bztsrc@github)
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "gpio.h" // get MMIO_BASE
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#include "uart.h"
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#define PAGESIZE 4096
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// granularity
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#define PT_PAGE 0b11 // 4k granule
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#define PT_BLOCK 0b01 // 2M granule
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// accessibility
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#define PT_KERNEL (0<<6) // privileged, supervisor EL1 access only
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#define PT_USER (1<<6) // unprivileged, EL0 access allowed
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#define PT_RW (0<<7) // read-write
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#define PT_RO (1<<7) // read-only
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#define PT_AF (1<<10) // accessed flag
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#define PT_NX (1UL<<54) // no execute
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// shareability
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#define PT_OSH (2<<8) // outter shareable
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#define PT_ISH (3<<8) // inner shareable
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// defined in MAIR register
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#define PT_MEM (0<<2) // normal memory
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#define PT_DEV (1<<2) // device MMIO
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#define PT_NC (2<<2) // non-cachable
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#define TTBR_ENABLE 1
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// get addresses from linker
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extern volatile unsigned char _data;
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extern volatile unsigned char _end;
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/**
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* Set up page translation tables and enable virtual memory
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*/
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void mmu_init()
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{
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unsigned long r, b, *paging=(unsigned long*)&_end;
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/* create MMU translation tables at _end */
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// TTBR0, identity L1
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paging[0]=(unsigned long)((unsigned char*)&_end+2*PAGESIZE) | // physical address
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PT_PAGE | // it has the "Present" flag, which must be set, and we have area in it mapped by pages
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PT_AF | // accessed flag. Without this we're going to have a Data Abort exception
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PT_USER | // non-privileged
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PT_ISH | // inner shareable
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PT_MEM; // normal memory
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// identity L2, first 2M block
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paging[2*512]=(unsigned long)((unsigned char*)&_end+3*PAGESIZE) | // physical address
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PT_PAGE | // we have area in it mapped by pages
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PT_AF | // accessed flag
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PT_USER | // non-privileged
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PT_ISH | // inner shareable
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PT_MEM; // normal memory
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// identity L2 2M blocks
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b=MMIO_BASE>>21;
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// skip 0th, as we're about to map it by L3
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for(r=1;r<512;r++)
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paging[2*512+r]=(unsigned long)((r<<21)) | // physical address
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PT_BLOCK | // map 2M block
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PT_AF | // accessed flag
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PT_NX | // no execute
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PT_USER | // non-privileged
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(r>=b? PT_OSH|PT_DEV : PT_ISH|PT_MEM); // different attributes for device memory
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// identity L3
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for(r=0;r<512;r++)
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paging[3*512+r]=(unsigned long)(r*PAGESIZE) | // physical address
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PT_PAGE | // map 4k
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PT_AF | // accessed flag
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PT_USER | // non-privileged
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PT_ISH | // inner shareable
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((r<0x80||r>(unsigned long)&_data/PAGESIZE)? PT_RW|PT_NX : PT_RO); // different for code and data
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// TTBR1, kernel L1
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paging[512+511]=(unsigned long)((unsigned char*)&_end+4*PAGESIZE) | // physical address
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PT_PAGE | // we have area in it mapped by pages
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PT_AF | // accessed flag
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PT_KERNEL | // privileged
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PT_ISH | // inner shareable
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PT_MEM; // normal memory
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// kernel L2
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paging[4*512+511]=(unsigned long)((unsigned char*)&_end+5*PAGESIZE) | // physical address
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PT_PAGE | // we have area in it mapped by pages
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PT_AF | // accessed flag
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PT_KERNEL | // privileged
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PT_ISH | // inner shareable
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PT_MEM; // normal memory
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// kernel L3
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paging[5*512]=(unsigned long)(MMIO_BASE+0x00201000) | // physical address
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PT_PAGE | // map 4k
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PT_AF | // accessed flag
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PT_NX | // no execute
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PT_KERNEL | // privileged
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PT_OSH | // outter shareable
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PT_DEV; // device memory
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/* okay, now we have to set system registers to enable MMU */
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// check for 4k granule and at least 36 bits physical address bus */
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asm volatile ("mrs %0, id_aa64mmfr0_el1" : "=r" (r));
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b=r&0xF;
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if(r&(0xF<<28)/*4k*/ || b<1/*36 bits*/) {
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uart_puts("ERROR: 4k granule or 36 bit address space not supported\n");
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return;
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}
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// first, set Memory Attributes array, indexed by PT_MEM, PT_DEV, PT_NC in our example
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r= (0xFF << 0) | // AttrIdx=0: normal, IWBWA, OWBWA, NTR
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(0x04 << 8) | // AttrIdx=1: device, nGnRE (must be OSH too)
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(0x44 <<16); // AttrIdx=2: non cacheable
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asm volatile ("msr mair_el1, %0" : : "r" (r));
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// next, specify mapping characteristics in translate control register
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r= (0b00LL << 37) | // TBI=0, no tagging
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(b << 32) | // IPS=autodetected
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(0b10LL << 30) | // TG1=4k
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(0b11LL << 28) | // SH1=3 inner
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(0b01LL << 26) | // ORGN1=1 write back
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(0b01LL << 24) | // IRGN1=1 write back
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(0b0LL << 23) | // EPD1 enable higher half
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(25LL << 16) | // T1SZ=25, 3 levels (512G)
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(0b00LL << 14) | // TG0=4k
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(0b11LL << 12) | // SH0=3 inner
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(0b01LL << 10) | // ORGN0=1 write back
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(0b01LL << 8) | // IRGN0=1 write back
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(0b0LL << 7) | // EPD0 enable lower half
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(25LL << 0); // T0SZ=25, 3 levels (512G)
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asm volatile ("msr tcr_el1, %0; isb" : : "r" (r));
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// tell the MMU where our translation tables are. TTBR_ENABLE bit not documented, but required
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// lower half, user space
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asm volatile ("msr ttbr0_el1, %0" : : "r" ((unsigned long)&_end + TTBR_ENABLE));
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// upper half, kernel space
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asm volatile ("msr ttbr1_el1, %0" : : "r" ((unsigned long)&_end + TTBR_ENABLE + PAGESIZE));
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// finally, toggle some bits in system control register to enable page translation
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asm volatile ("dsb ish; isb; mrs %0, sctlr_el1" : "=r" (r));
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r|=0xC00800; // set mandatory reserved bits
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r&=~((1<<25) | // clear EE, little endian translation tables
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(1<<24) | // clear E0E
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(1<<19) | // clear WXN
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(1<<12) | // clear I, no instruction cache
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(1<<4) | // clear SA0
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(1<<3) | // clear SA
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(1<<2) | // clear C, no cache at all
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(1<<1)); // clear A, no aligment check
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r|= (1<<0); // set M, enable MMU
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asm volatile ("msr sctlr_el1, %0; isb" : : "r" (r));
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}
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