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314 lines
9.9 KiB
Rust
314 lines
9.9 KiB
Rust
// SPDX-License-Identifier: MIT OR Apache-2.0
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//
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// Copyright (c) 2018-2022 Andre Richter <andre.o.richter@gmail.com>
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//! Architectural synchronous and asynchronous exception handling.
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//!
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//! # Orientation
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//!
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//! Since arch modules are imported into generic modules using the path attribute, the path of this
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//! file is:
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//!
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//! crate::exception::arch_exception
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use crate::exception;
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use core::{arch::global_asm, cell::UnsafeCell, fmt};
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use cortex_a::{asm::barrier, registers::*};
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use tock_registers::{
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interfaces::{Readable, Writeable},
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registers::InMemoryRegister,
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};
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// Assembly counterpart to this file.
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global_asm!(include_str!("exception.s"));
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//--------------------------------------------------------------------------------------------------
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// Private Definitions
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//--------------------------------------------------------------------------------------------------
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/// Wrapper structs for memory copies of registers.
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#[repr(transparent)]
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struct SpsrEL1(InMemoryRegister<u64, SPSR_EL1::Register>);
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struct EsrEL1(InMemoryRegister<u64, ESR_EL1::Register>);
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/// The exception context as it is stored on the stack on exception entry.
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#[repr(C)]
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struct ExceptionContext {
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/// General Purpose Registers.
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gpr: [u64; 30],
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/// The link register, aka x30.
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lr: u64,
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/// Exception link register. The program counter at the time the exception happened.
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elr_el1: u64,
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/// Saved program status.
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spsr_el1: SpsrEL1,
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/// Exception syndrome register.
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esr_el1: EsrEL1,
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}
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//--------------------------------------------------------------------------------------------------
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// Private Code
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//--------------------------------------------------------------------------------------------------
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/// Prints verbose information about the exception and then panics.
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fn default_exception_handler(exc: &ExceptionContext) {
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panic!(
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"CPU Exception!\n\n\
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{}",
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exc
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);
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}
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//------------------------------------------------------------------------------
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// Current, EL0
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//------------------------------------------------------------------------------
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#[no_mangle]
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unsafe extern "C" fn current_el0_synchronous(_e: &mut ExceptionContext) {
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panic!("Should not be here. Use of SP_EL0 in EL1 is not supported.")
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}
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#[no_mangle]
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unsafe extern "C" fn current_el0_irq(_e: &mut ExceptionContext) {
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panic!("Should not be here. Use of SP_EL0 in EL1 is not supported.")
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}
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#[no_mangle]
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unsafe extern "C" fn current_el0_serror(_e: &mut ExceptionContext) {
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panic!("Should not be here. Use of SP_EL0 in EL1 is not supported.")
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}
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//------------------------------------------------------------------------------
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// Current, ELx
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//------------------------------------------------------------------------------
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#[no_mangle]
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unsafe extern "C" fn current_elx_synchronous(e: &mut ExceptionContext) {
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#[cfg(feature = "test_build")]
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{
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const TEST_SVC_ID: u64 = 0x1337;
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if let Some(ESR_EL1::EC::Value::SVC64) = e.esr_el1.exception_class() {
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if e.esr_el1.iss() == TEST_SVC_ID {
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return;
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}
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}
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}
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default_exception_handler(e);
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}
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#[no_mangle]
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unsafe extern "C" fn current_elx_irq(_e: &mut ExceptionContext) {
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let token = &exception::asynchronous::IRQContext::new();
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exception::asynchronous::irq_manager().handle_pending_irqs(token);
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}
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#[no_mangle]
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unsafe extern "C" fn current_elx_serror(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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//------------------------------------------------------------------------------
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// Lower, AArch64
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//------------------------------------------------------------------------------
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#[no_mangle]
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unsafe extern "C" fn lower_aarch64_synchronous(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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#[no_mangle]
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unsafe extern "C" fn lower_aarch64_irq(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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#[no_mangle]
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unsafe extern "C" fn lower_aarch64_serror(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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//------------------------------------------------------------------------------
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// Lower, AArch32
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//------------------------------------------------------------------------------
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#[no_mangle]
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unsafe extern "C" fn lower_aarch32_synchronous(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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#[no_mangle]
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unsafe extern "C" fn lower_aarch32_irq(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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#[no_mangle]
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unsafe extern "C" fn lower_aarch32_serror(e: &mut ExceptionContext) {
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default_exception_handler(e);
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}
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//------------------------------------------------------------------------------
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// Misc
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//------------------------------------------------------------------------------
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/// Human readable SPSR_EL1.
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#[rustfmt::skip]
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impl fmt::Display for SpsrEL1 {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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// Raw value.
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writeln!(f, "SPSR_EL1: {:#010x}", self.0.get())?;
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let to_flag_str = |x| -> _ {
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if x { "Set" } else { "Not set" }
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};
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writeln!(f, " Flags:")?;
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writeln!(f, " Negative (N): {}", to_flag_str(self.0.is_set(SPSR_EL1::N)))?;
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writeln!(f, " Zero (Z): {}", to_flag_str(self.0.is_set(SPSR_EL1::Z)))?;
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writeln!(f, " Carry (C): {}", to_flag_str(self.0.is_set(SPSR_EL1::C)))?;
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writeln!(f, " Overflow (V): {}", to_flag_str(self.0.is_set(SPSR_EL1::V)))?;
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let to_mask_str = |x| -> _ {
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if x { "Masked" } else { "Unmasked" }
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};
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writeln!(f, " Exception handling state:")?;
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writeln!(f, " Debug (D): {}", to_mask_str(self.0.is_set(SPSR_EL1::D)))?;
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writeln!(f, " SError (A): {}", to_mask_str(self.0.is_set(SPSR_EL1::A)))?;
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writeln!(f, " IRQ (I): {}", to_mask_str(self.0.is_set(SPSR_EL1::I)))?;
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writeln!(f, " FIQ (F): {}", to_mask_str(self.0.is_set(SPSR_EL1::F)))?;
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write!(f, " Illegal Execution State (IL): {}",
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to_flag_str(self.0.is_set(SPSR_EL1::IL))
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)
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}
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}
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impl EsrEL1 {
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#[inline(always)]
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fn exception_class(&self) -> Option<ESR_EL1::EC::Value> {
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self.0.read_as_enum(ESR_EL1::EC)
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}
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#[cfg(feature = "test_build")]
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#[inline(always)]
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fn iss(&self) -> u64 {
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self.0.read(ESR_EL1::ISS)
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}
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}
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/// Human readable ESR_EL1.
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#[rustfmt::skip]
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impl fmt::Display for EsrEL1 {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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// Raw print of whole register.
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writeln!(f, "ESR_EL1: {:#010x}", self.0.get())?;
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// Raw print of exception class.
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write!(f, " Exception Class (EC) : {:#x}", self.0.read(ESR_EL1::EC))?;
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// Exception class.
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let ec_translation = match self.exception_class() {
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Some(ESR_EL1::EC::Value::DataAbortCurrentEL) => "Data Abort, current EL",
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_ => "N/A",
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};
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writeln!(f, " - {}", ec_translation)?;
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// Raw print of instruction specific syndrome.
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write!(f, " Instr Specific Syndrome (ISS): {:#x}", self.0.read(ESR_EL1::ISS))
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}
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}
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impl ExceptionContext {
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#[inline(always)]
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fn exception_class(&self) -> Option<ESR_EL1::EC::Value> {
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self.esr_el1.exception_class()
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}
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#[inline(always)]
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fn fault_address_valid(&self) -> bool {
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use ESR_EL1::EC::Value::*;
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match self.exception_class() {
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None => false,
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Some(ec) => matches!(
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ec,
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InstrAbortLowerEL
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| InstrAbortCurrentEL
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| PCAlignmentFault
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| DataAbortLowerEL
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| DataAbortCurrentEL
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| WatchpointLowerEL
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| WatchpointCurrentEL
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),
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}
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}
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}
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/// Human readable print of the exception context.
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impl fmt::Display for ExceptionContext {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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writeln!(f, "{}", self.esr_el1)?;
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if self.fault_address_valid() {
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writeln!(f, "FAR_EL1: {:#018x}", FAR_EL1.get() as usize)?;
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}
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writeln!(f, "{}", self.spsr_el1)?;
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writeln!(f, "ELR_EL1: {:#018x}", self.elr_el1)?;
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writeln!(f)?;
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writeln!(f, "General purpose register:")?;
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#[rustfmt::skip]
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let alternating = |x| -> _ {
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if x % 2 == 0 { " " } else { "\n" }
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};
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// Print two registers per line.
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for (i, reg) in self.gpr.iter().enumerate() {
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write!(f, " x{: <2}: {: >#018x}{}", i, reg, alternating(i))?;
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}
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write!(f, " lr : {:#018x}", self.lr)
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}
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}
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//--------------------------------------------------------------------------------------------------
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// Public Code
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//--------------------------------------------------------------------------------------------------
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use crate::exception::PrivilegeLevel;
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/// The processing element's current privilege level.
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pub fn current_privilege_level() -> (PrivilegeLevel, &'static str) {
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let el = CurrentEL.read_as_enum(CurrentEL::EL);
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match el {
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Some(CurrentEL::EL::Value::EL2) => (PrivilegeLevel::Hypervisor, "EL2"),
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Some(CurrentEL::EL::Value::EL1) => (PrivilegeLevel::Kernel, "EL1"),
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Some(CurrentEL::EL::Value::EL0) => (PrivilegeLevel::User, "EL0"),
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_ => (PrivilegeLevel::Unknown, "Unknown"),
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}
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}
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/// Init exception handling by setting the exception vector base address register.
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///
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/// # Safety
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///
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/// - Changes the HW state of the executing core.
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/// - The vector table and the symbol `__exception_vector_table_start` from the linker script must
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/// adhere to the alignment and size constraints demanded by the ARMv8-A Architecture Reference
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/// Manual.
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pub unsafe fn handling_init() {
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// Provided by exception.S.
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extern "Rust" {
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static __exception_vector_start: UnsafeCell<()>;
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}
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VBAR_EL1.set(__exception_vector_start.get() as u64);
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// Force VBAR update to complete before next instruction.
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barrier::isb(barrier::SY);
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}
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