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222 lines
8.6 KiB
Rust
222 lines
8.6 KiB
Rust
// SPDX-License-Identifier: MIT OR Apache-2.0
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//
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// Copyright (c) 2020-2022 Andre Richter <andre.o.richter@gmail.com>
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//! GICv2 Driver - ARM Generic Interrupt Controller v2.
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//!
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//! The following is a collection of excerpts with useful information from
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//! - `Programmer's Guide for ARMv8-A`
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//! - `ARM Generic Interrupt Controller Architecture Specification`
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//!
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//! # Programmer's Guide - 10.6.1 Configuration
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//!
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//! The GIC is accessed as a memory-mapped peripheral.
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//!
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//! All cores can access the common Distributor, but the CPU interface is banked, that is, each core
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//! uses the same address to access its own private CPU interface.
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//!
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//! It is not possible for a core to access the CPU interface of another core.
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//!
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//! # Architecture Specification - 10.6.2 Initialization
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//!
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//! Both the Distributor and the CPU interfaces are disabled at reset. The GIC must be initialized
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//! after reset before it can deliver interrupts to the core.
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//!
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//! In the Distributor, software must configure the priority, target, security and enable individual
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//! interrupts. The Distributor must subsequently be enabled through its control register
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//! (GICD_CTLR). For each CPU interface, software must program the priority mask and preemption
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//! settings.
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//!
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//! Each CPU interface block itself must be enabled through its control register (GICD_CTLR). This
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//! prepares the GIC to deliver interrupts to the core.
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//!
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//! Before interrupts are expected in the core, software prepares the core to take interrupts by
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//! setting a valid interrupt vector in the vector table, and clearing interrupt mask bits in
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//! PSTATE, and setting the routing controls.
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//!
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//! The entire interrupt mechanism in the system can be disabled by disabling the Distributor.
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//! Interrupt delivery to an individual core can be disabled by disabling its CPU interface.
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//! Individual interrupts can also be disabled (or enabled) in the distributor.
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//!
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//! For an interrupt to reach the core, the individual interrupt, Distributor and CPU interface must
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//! all be enabled. The interrupt also needs to be of sufficient priority, that is, higher than the
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//! core's priority mask.
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//!
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//! # Architecture Specification - 1.4.2 Interrupt types
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//!
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//! - Peripheral interrupt
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//! - Private Peripheral Interrupt (PPI)
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//! - This is a peripheral interrupt that is specific to a single processor.
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//! - Shared Peripheral Interrupt (SPI)
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//! - This is a peripheral interrupt that the Distributor can route to any of a specified
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//! combination of processors.
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//!
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//! - Software-generated interrupt (SGI)
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//! - This is an interrupt generated by software writing to a GICD_SGIR register in the GIC. The
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//! system uses SGIs for interprocessor communication.
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//! - An SGI has edge-triggered properties. The software triggering of the interrupt is
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//! equivalent to the edge transition of the interrupt request signal.
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//! - When an SGI occurs in a multiprocessor implementation, the CPUID field in the Interrupt
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//! Acknowledge Register, GICC_IAR, or the Aliased Interrupt Acknowledge Register, GICC_AIAR,
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//! identifies the processor that requested the interrupt.
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//!
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//! # Architecture Specification - 2.2.1 Interrupt IDs
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//!
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//! Interrupts from sources are identified using ID numbers. Each CPU interface can see up to 1020
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//! interrupts. The banking of SPIs and PPIs increases the total number of interrupts supported by
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//! the Distributor.
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//!
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//! The GIC assigns interrupt ID numbers ID0-ID1019 as follows:
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//! - Interrupt numbers 32..1019 are used for SPIs.
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//! - Interrupt numbers 0..31 are used for interrupts that are private to a CPU interface. These
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//! interrupts are banked in the Distributor.
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//! - A banked interrupt is one where the Distributor can have multiple interrupts with the
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//! same ID. A banked interrupt is identified uniquely by its ID number and its associated
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//! CPU interface number. Of the banked interrupt IDs:
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//! - 00..15 SGIs
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//! - 16..31 PPIs
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mod gicc;
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mod gicd;
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use crate::{bsp, cpu, driver, exception, synchronization, synchronization::InitStateLock};
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//--------------------------------------------------------------------------------------------------
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// Private Definitions
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//--------------------------------------------------------------------------------------------------
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type HandlerTable = [Option<exception::asynchronous::IRQDescriptor>; GICv2::NUM_IRQS];
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//--------------------------------------------------------------------------------------------------
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// Public Definitions
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//--------------------------------------------------------------------------------------------------
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/// Used for the associated type of trait [`exception::asynchronous::interface::IRQManager`].
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pub type IRQNumber = exception::asynchronous::IRQNumber<{ GICv2::MAX_IRQ_NUMBER }>;
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/// Representation of the GIC.
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pub struct GICv2 {
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/// The Distributor.
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gicd: gicd::GICD,
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/// The CPU Interface.
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gicc: gicc::GICC,
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/// Stores registered IRQ handlers. Writable only during kernel init. RO afterwards.
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handler_table: InitStateLock<HandlerTable>,
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}
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//--------------------------------------------------------------------------------------------------
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// Public Code
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//--------------------------------------------------------------------------------------------------
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impl GICv2 {
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const MAX_IRQ_NUMBER: usize = 300; // Normally 1019, but keep it lower to save some space.
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const NUM_IRQS: usize = Self::MAX_IRQ_NUMBER + 1;
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pub const COMPATIBLE: &'static str = "GICv2 (ARM Generic Interrupt Controller v2)";
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/// Create an instance.
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///
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/// # Safety
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///
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/// - The user must ensure to provide a correct MMIO start address.
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pub const unsafe fn new(gicd_mmio_start_addr: usize, gicc_mmio_start_addr: usize) -> Self {
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Self {
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gicd: gicd::GICD::new(gicd_mmio_start_addr),
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gicc: gicc::GICC::new(gicc_mmio_start_addr),
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handler_table: InitStateLock::new([None; Self::NUM_IRQS]),
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}
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}
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}
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//------------------------------------------------------------------------------
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// OS Interface Code
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//------------------------------------------------------------------------------
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use synchronization::interface::ReadWriteEx;
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impl driver::interface::DeviceDriver for GICv2 {
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fn compatible(&self) -> &'static str {
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Self::COMPATIBLE
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}
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unsafe fn init(&self) -> Result<(), &'static str> {
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if bsp::cpu::BOOT_CORE_ID == cpu::smp::core_id() {
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self.gicd.boot_core_init();
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}
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self.gicc.priority_accept_all();
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self.gicc.enable();
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Ok(())
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}
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}
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impl exception::asynchronous::interface::IRQManager for GICv2 {
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type IRQNumberType = IRQNumber;
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fn register_handler(
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&self,
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irq_number: Self::IRQNumberType,
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descriptor: exception::asynchronous::IRQDescriptor,
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) -> Result<(), &'static str> {
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self.handler_table.write(|table| {
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let irq_number = irq_number.get();
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if table[irq_number].is_some() {
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return Err("IRQ handler already registered");
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}
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table[irq_number] = Some(descriptor);
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Ok(())
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})
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}
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fn enable(&self, irq_number: Self::IRQNumberType) {
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self.gicd.enable(irq_number);
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}
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fn handle_pending_irqs<'irq_context>(
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&'irq_context self,
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ic: &exception::asynchronous::IRQContext<'irq_context>,
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) {
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// Extract the highest priority pending IRQ number from the Interrupt Acknowledge Register
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// (IAR).
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let irq_number = self.gicc.pending_irq_number(ic);
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// Guard against spurious interrupts.
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if irq_number > GICv2::MAX_IRQ_NUMBER {
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return;
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}
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// Call the IRQ handler. Panic if there is none.
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self.handler_table.read(|table| {
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match table[irq_number] {
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None => panic!("No handler registered for IRQ {}", irq_number),
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Some(descriptor) => {
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// Call the IRQ handler. Panics on failure.
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descriptor.handler.handle().expect("Error handling IRQ");
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}
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}
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});
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// Signal completion of handling.
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self.gicc.mark_comleted(irq_number as u32, ic);
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}
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fn print_handler(&self) {
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use crate::info;
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info!(" Peripheral handler:");
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self.handler_table.read(|table| {
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for (i, opt) in table.iter().skip(32).enumerate() {
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if let Some(handler) = opt {
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info!(" {: >3}. {}", i + 32, handler.name);
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}
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}
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});
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}
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}
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