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@ -163,22 +163,8 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
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*/
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if (mp1_intr)
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{
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smu_wait(adev);
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/* disallowgfx_off or something */
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vr_info(dev, "gfx off\n");
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0x00);
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, 0x00);
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, 0x2A);
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smu_wait(adev);
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/* stop SMC */
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vr_info(dev, "Prep Reset\n");
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0x00);
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, 0x00);
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/* PPSMC_MSG_PrepareMp1ForReset */
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, 0x33);
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smu_wait(adev);
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smum_send_msg_to_smc(adev, PPSMC_MSG_DisallowGfxOff, NULL);
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smum_send_msg_to_smc(adev, PPSMC_MSG_PrepareMp1ForReset, NULL);
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}
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vr_info(dev, "begin psp mode 1 reset\n");
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@ -187,19 +173,16 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
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pci_save_state(dev->pdev);
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/* check validity of PSP before reset */
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vr_info(dev, "PSP wait\n");
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offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
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tmp = psp_wait_for(adev, offset, 0x80000000, 0x8000FFFF, false);
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if (tmp)
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vr_warn(dev, "timed out waiting for PSP to reach valid state, but continuing anyway\n");
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/* reset command */
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vr_info(dev, "do mode1 reset\n");
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_MODE1_RST);
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msleep(500);
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/* wait for ACK */
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vr_info(dev, "PSP wait\n");
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offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
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tmp = psp_wait_for(adev, offset, 0x80000000, 0x80000000, false);
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if (tmp)
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@ -221,7 +204,6 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
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break;
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udelay(1);
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}
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vr_info(dev, "memsize: %x\n", tmp);
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/*
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* this takes a long time :(
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@ -231,10 +213,6 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
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/* see if PSP bootloader comes back */
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if (RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L)
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break;
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vr_info(dev, "PSP bootloader flags? %x, timeout: %s\n",
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RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35), !timeout ? "yes" : "no");
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msleep(100);
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}
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@ -246,9 +224,8 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
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else
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vr_info(dev, "PSP mode1 reset successful\n");
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pci_restore_state(dev->pdev);
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out:
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pci_restore_state(dev->pdev);
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amdgpu_atombios_scratch_regs_engine_hung(adev, false);
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free_adev:
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@ -259,7 +236,7 @@ free_adev:
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const struct vendor_reset_ops amd_navi10_ops =
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{
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.version = {1, 0},
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.version = {1, 1},
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.probe = amd_common_probe,
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.pre_reset = amd_common_pre_reset,
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.reset = amd_navi10_reset,
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