From 8d5922b43489602dacfb06a19de54702522e06e8 Mon Sep 17 00:00:00 2001 From: Adam Madsen Date: Tue, 10 Nov 2020 09:36:05 -0600 Subject: [PATCH] AMD: I think that's Navi. --- .gitignore | 1 + src/amd/Makefile | 2 + src/amd/amd.h | 21 +- src/amd/amdgpu/include/navi12_ip_offset.h | 1119 ++++++++++ src/amd/amdgpu/include/navi14_ip_offset.h | 1116 ++++++++++ src/amd/amdgpu/include/smu_v11_0.h | 57 + src/amd/amdgpu/include/vega10_ip_offset.h | 2461 ++++++++++----------- src/amd/amdgpu/navi12_reg_init.c | 53 + src/amd/amdgpu/navi14_reg_init.c | 54 + src/amd/common.c | 43 +- src/amd/common.h | 8 +- src/amd/navi10.c | 214 +- src/amd/polaris10.c | 18 +- src/amd/vega10.c | 7 +- src/device-db.h | 161 +- src/hooks.c | 1 + src/vendor-reset-dev.h | 4 + src/vendor-reset.c | 1 + 18 files changed, 3998 insertions(+), 1343 deletions(-) create mode 100644 src/amd/amdgpu/include/navi12_ip_offset.h create mode 100644 src/amd/amdgpu/include/navi14_ip_offset.h create mode 100644 src/amd/amdgpu/include/smu_v11_0.h create mode 100644 src/amd/amdgpu/navi12_reg_init.c create mode 100644 src/amd/amdgpu/navi14_reg_init.c diff --git a/.gitignore b/.gitignore index 8323ab7..346e083 100644 --- a/.gitignore +++ b/.gitignore @@ -5,3 +5,4 @@ *.o *.symvers *.order +*.d diff --git a/src/amd/Makefile b/src/amd/Makefile index d7ebb31..f494af0 100644 --- a/src/amd/Makefile +++ b/src/amd/Makefile @@ -9,6 +9,8 @@ vendor-reset-y += \ src/amd/amdgpu/common_baco.o \ src/amd/amdgpu/vega10_reg_init.o \ src/amd/amdgpu/navi10_reg_init.o \ + src/amd/amdgpu/navi12_reg_init.o \ + src/amd/amdgpu/navi14_reg_init.o \ src/amd/amdgpu/amdgpu_device.o \ src/amd/amdgpu/amdgpu_discovery.o \ src/amd/amdgpu/atom.o \ diff --git a/src/amd/amd.h b/src/amd/amd.h index cc4b224..9c135c6 100644 --- a/src/amd/amd.h +++ b/src/amd/amd.h @@ -16,7 +16,20 @@ this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -extern struct vendor_reset_ops amd_polaris10_ops; -extern struct vendor_reset_ops amd_vega10_ops; -extern struct vendor_reset_ops amd_vega20_ops; -extern struct vendor_reset_ops amd_navi10_ops; +enum amd_device_type +{ + AMD_POLARIS10, + AMD_POLARIS11, + AMD_POLARIS12, + AMD_VEGA10, + AMD_VEGA12, + AMD_VEGA20, + AMD_NAVI10, + AMD_NAVI12, + AMD_NAVI14, +}; + +extern const struct vendor_reset_ops amd_polaris10_ops; +extern const struct vendor_reset_ops amd_vega10_ops; +extern const struct vendor_reset_ops amd_vega20_ops; +extern const struct vendor_reset_ops amd_navi10_ops; diff --git a/src/amd/amdgpu/include/navi12_ip_offset.h b/src/amd/amdgpu/include/navi12_ip_offset.h new file mode 100644 index 0000000..6c2cc62 --- /dev/null +++ b/src/amd/amdgpu/include/navi12_ip_offset.h @@ -0,0 +1,1119 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _navi12_ip_offset_HEADER +#define _navi12_ip_offset_HEADER + +#define MAX_INSTANCE 7 +#define MAX_SEGMENT 5 + + +struct IP_BASE_INSTANCE +{ + unsigned int segment[MAX_SEGMENT]; +}; + +struct IP_BASE +{ + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; +}; + + +static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, + { { 0x00016E00, 0x02401C00, 0, 0, 0 } }, + { { 0x00017000, 0x02402000, 0, 0, 0 } }, + { { 0x00017200, 0x02402400, 0, 0, 0 } }, + { { 0x0001B000, 0x0242D800, 0, 0, 0 } }, + { { 0x00017E00, 0x0240BC00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE HDA_BASE ={ { { { 0x004C0000, 0x02404800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00E80000, 0x00EC0000, 0x00F00000, 0x02400400 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, + { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } }, + { { 0x00054000, 0x02425C00, 0, 0, 0 } }, + { { 0x00094000, 0x02426000, 0, 0, 0 } }, + { { 0x000D4000, 0x02426400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; + + +#define ATHUB_BASE__INST0_SEG0 0x00000C00 +#define ATHUB_BASE__INST0_SEG1 0x02408C00 +#define ATHUB_BASE__INST0_SEG2 0 +#define ATHUB_BASE__INST0_SEG3 0 +#define ATHUB_BASE__INST0_SEG4 0 + +#define ATHUB_BASE__INST1_SEG0 0 +#define ATHUB_BASE__INST1_SEG1 0 +#define ATHUB_BASE__INST1_SEG2 0 +#define ATHUB_BASE__INST1_SEG3 0 +#define ATHUB_BASE__INST1_SEG4 0 + +#define ATHUB_BASE__INST2_SEG0 0 +#define ATHUB_BASE__INST2_SEG1 0 +#define ATHUB_BASE__INST2_SEG2 0 +#define ATHUB_BASE__INST2_SEG3 0 +#define ATHUB_BASE__INST2_SEG4 0 + +#define ATHUB_BASE__INST3_SEG0 0 +#define ATHUB_BASE__INST3_SEG1 0 +#define ATHUB_BASE__INST3_SEG2 0 +#define ATHUB_BASE__INST3_SEG3 0 +#define ATHUB_BASE__INST3_SEG4 0 + +#define ATHUB_BASE__INST4_SEG0 0 +#define ATHUB_BASE__INST4_SEG1 0 +#define ATHUB_BASE__INST4_SEG2 0 +#define ATHUB_BASE__INST4_SEG3 0 +#define ATHUB_BASE__INST4_SEG4 0 + +#define ATHUB_BASE__INST5_SEG0 0 +#define ATHUB_BASE__INST5_SEG1 0 +#define ATHUB_BASE__INST5_SEG2 0 +#define ATHUB_BASE__INST5_SEG3 0 +#define ATHUB_BASE__INST5_SEG4 0 + +#define ATHUB_BASE__INST6_SEG0 0 +#define ATHUB_BASE__INST6_SEG1 0 +#define ATHUB_BASE__INST6_SEG2 0 +#define ATHUB_BASE__INST6_SEG3 0 +#define ATHUB_BASE__INST6_SEG4 0 + +#define CLK_BASE__INST0_SEG0 0x00016C00 +#define CLK_BASE__INST0_SEG1 0x02401800 +#define CLK_BASE__INST0_SEG2 0 +#define CLK_BASE__INST0_SEG3 0 +#define CLK_BASE__INST0_SEG4 0 + +#define CLK_BASE__INST1_SEG0 0x00016E00 +#define CLK_BASE__INST1_SEG1 0x02401C00 +#define CLK_BASE__INST1_SEG2 0 +#define CLK_BASE__INST1_SEG3 0 +#define CLK_BASE__INST1_SEG4 0 + +#define CLK_BASE__INST2_SEG0 0x00017000 +#define CLK_BASE__INST2_SEG1 0x02402000 +#define CLK_BASE__INST2_SEG2 0 +#define CLK_BASE__INST2_SEG3 0 +#define CLK_BASE__INST2_SEG4 0 + +#define CLK_BASE__INST3_SEG0 0x00017200 +#define CLK_BASE__INST3_SEG1 0x02402400 +#define CLK_BASE__INST3_SEG2 0 +#define CLK_BASE__INST3_SEG3 0 +#define CLK_BASE__INST3_SEG4 0 + +#define CLK_BASE__INST4_SEG0 0x0001B000 +#define CLK_BASE__INST4_SEG1 0x0242D800 +#define CLK_BASE__INST4_SEG2 0 +#define CLK_BASE__INST4_SEG3 0 +#define CLK_BASE__INST4_SEG4 0 + +#define CLK_BASE__INST5_SEG0 0x00017E00 +#define CLK_BASE__INST5_SEG1 0x0240BC00 +#define CLK_BASE__INST5_SEG2 0 +#define CLK_BASE__INST5_SEG3 0 +#define CLK_BASE__INST5_SEG4 0 + +#define CLK_BASE__INST6_SEG0 0 +#define CLK_BASE__INST6_SEG1 0 +#define CLK_BASE__INST6_SEG2 0 +#define CLK_BASE__INST6_SEG3 0 +#define CLK_BASE__INST6_SEG4 0 + +#define DF_BASE__INST0_SEG0 0x00007000 +#define DF_BASE__INST0_SEG1 0x0240B800 +#define DF_BASE__INST0_SEG2 0 +#define DF_BASE__INST0_SEG3 0 +#define DF_BASE__INST0_SEG4 0 + +#define DF_BASE__INST1_SEG0 0 +#define DF_BASE__INST1_SEG1 0 +#define DF_BASE__INST1_SEG2 0 +#define DF_BASE__INST1_SEG3 0 +#define DF_BASE__INST1_SEG4 0 + +#define DF_BASE__INST2_SEG0 0 +#define DF_BASE__INST2_SEG1 0 +#define DF_BASE__INST2_SEG2 0 +#define DF_BASE__INST2_SEG3 0 +#define DF_BASE__INST2_SEG4 0 + +#define DF_BASE__INST3_SEG0 0 +#define DF_BASE__INST3_SEG1 0 +#define DF_BASE__INST3_SEG2 0 +#define DF_BASE__INST3_SEG3 0 +#define DF_BASE__INST3_SEG4 0 + +#define DF_BASE__INST4_SEG0 0 +#define DF_BASE__INST4_SEG1 0 +#define DF_BASE__INST4_SEG2 0 +#define DF_BASE__INST4_SEG3 0 +#define DF_BASE__INST4_SEG4 0 + +#define DF_BASE__INST5_SEG0 0 +#define DF_BASE__INST5_SEG1 0 +#define DF_BASE__INST5_SEG2 0 +#define DF_BASE__INST5_SEG3 0 +#define DF_BASE__INST5_SEG4 0 + +#define DF_BASE__INST6_SEG0 0 +#define DF_BASE__INST6_SEG1 0 +#define DF_BASE__INST6_SEG2 0 +#define DF_BASE__INST6_SEG3 0 +#define DF_BASE__INST6_SEG4 0 + +#define DIO_BASE__INST0_SEG0 0x02404000 +#define DIO_BASE__INST0_SEG1 0 +#define DIO_BASE__INST0_SEG2 0 +#define DIO_BASE__INST0_SEG3 0 +#define DIO_BASE__INST0_SEG4 0 + +#define DIO_BASE__INST1_SEG0 0 +#define DIO_BASE__INST1_SEG1 0 +#define DIO_BASE__INST1_SEG2 0 +#define DIO_BASE__INST1_SEG3 0 +#define DIO_BASE__INST1_SEG4 0 + +#define DIO_BASE__INST2_SEG0 0 +#define DIO_BASE__INST2_SEG1 0 +#define DIO_BASE__INST2_SEG2 0 +#define DIO_BASE__INST2_SEG3 0 +#define DIO_BASE__INST2_SEG4 0 + +#define DIO_BASE__INST3_SEG0 0 +#define DIO_BASE__INST3_SEG1 0 +#define DIO_BASE__INST3_SEG2 0 +#define DIO_BASE__INST3_SEG3 0 +#define DIO_BASE__INST3_SEG4 0 + +#define DIO_BASE__INST4_SEG0 0 +#define DIO_BASE__INST4_SEG1 0 +#define DIO_BASE__INST4_SEG2 0 +#define DIO_BASE__INST4_SEG3 0 +#define DIO_BASE__INST4_SEG4 0 + +#define DIO_BASE__INST5_SEG0 0 +#define DIO_BASE__INST5_SEG1 0 +#define DIO_BASE__INST5_SEG2 0 +#define DIO_BASE__INST5_SEG3 0 +#define DIO_BASE__INST5_SEG4 0 + +#define DIO_BASE__INST6_SEG0 0 +#define DIO_BASE__INST6_SEG1 0 +#define DIO_BASE__INST6_SEG2 0 +#define DIO_BASE__INST6_SEG3 0 +#define DIO_BASE__INST6_SEG4 0 + +#define DMU_BASE__INST0_SEG0 0x00000012 +#define DMU_BASE__INST0_SEG1 0x000000C0 +#define DMU_BASE__INST0_SEG2 0x000034C0 +#define DMU_BASE__INST0_SEG3 0x00009000 +#define DMU_BASE__INST0_SEG4 0x02403C00 + +#define DMU_BASE__INST1_SEG0 0 +#define DMU_BASE__INST1_SEG1 0 +#define DMU_BASE__INST1_SEG2 0 +#define DMU_BASE__INST1_SEG3 0 +#define DMU_BASE__INST1_SEG4 0 + +#define DMU_BASE__INST2_SEG0 0 +#define DMU_BASE__INST2_SEG1 0 +#define DMU_BASE__INST2_SEG2 0 +#define DMU_BASE__INST2_SEG3 0 +#define DMU_BASE__INST2_SEG4 0 + +#define DMU_BASE__INST3_SEG0 0 +#define DMU_BASE__INST3_SEG1 0 +#define DMU_BASE__INST3_SEG2 0 +#define DMU_BASE__INST3_SEG3 0 +#define DMU_BASE__INST3_SEG4 0 + +#define DMU_BASE__INST4_SEG0 0 +#define DMU_BASE__INST4_SEG1 0 +#define DMU_BASE__INST4_SEG2 0 +#define DMU_BASE__INST4_SEG3 0 +#define DMU_BASE__INST4_SEG4 0 + +#define DMU_BASE__INST5_SEG0 0 +#define DMU_BASE__INST5_SEG1 0 +#define DMU_BASE__INST5_SEG2 0 +#define DMU_BASE__INST5_SEG3 0 +#define DMU_BASE__INST5_SEG4 0 + +#define DMU_BASE__INST6_SEG0 0 +#define DMU_BASE__INST6_SEG1 0 +#define DMU_BASE__INST6_SEG2 0 +#define DMU_BASE__INST6_SEG3 0 +#define DMU_BASE__INST6_SEG4 0 + +#define DPCS_BASE__INST0_SEG0 0x00000012 +#define DPCS_BASE__INST0_SEG1 0x000000C0 +#define DPCS_BASE__INST0_SEG2 0x000034C0 +#define DPCS_BASE__INST0_SEG3 0x00009000 +#define DPCS_BASE__INST0_SEG4 0x02403C00 + +#define DPCS_BASE__INST1_SEG0 0 +#define DPCS_BASE__INST1_SEG1 0 +#define DPCS_BASE__INST1_SEG2 0 +#define DPCS_BASE__INST1_SEG3 0 +#define DPCS_BASE__INST1_SEG4 0 + +#define DPCS_BASE__INST2_SEG0 0 +#define DPCS_BASE__INST2_SEG1 0 +#define DPCS_BASE__INST2_SEG2 0 +#define DPCS_BASE__INST2_SEG3 0 +#define DPCS_BASE__INST2_SEG4 0 + +#define DPCS_BASE__INST3_SEG0 0 +#define DPCS_BASE__INST3_SEG1 0 +#define DPCS_BASE__INST3_SEG2 0 +#define DPCS_BASE__INST3_SEG3 0 +#define DPCS_BASE__INST3_SEG4 0 + +#define DPCS_BASE__INST4_SEG0 0 +#define DPCS_BASE__INST4_SEG1 0 +#define DPCS_BASE__INST4_SEG2 0 +#define DPCS_BASE__INST4_SEG3 0 +#define DPCS_BASE__INST4_SEG4 0 + +#define DPCS_BASE__INST5_SEG0 0 +#define DPCS_BASE__INST5_SEG1 0 +#define DPCS_BASE__INST5_SEG2 0 +#define DPCS_BASE__INST5_SEG3 0 +#define DPCS_BASE__INST5_SEG4 0 + +#define DPCS_BASE__INST6_SEG0 0 +#define DPCS_BASE__INST6_SEG1 0 +#define DPCS_BASE__INST6_SEG2 0 +#define DPCS_BASE__INST6_SEG3 0 +#define DPCS_BASE__INST6_SEG4 0 + +#define FUSE_BASE__INST0_SEG0 0x00017400 +#define FUSE_BASE__INST0_SEG1 0x02401400 +#define FUSE_BASE__INST0_SEG2 0 +#define FUSE_BASE__INST0_SEG3 0 +#define FUSE_BASE__INST0_SEG4 0 + +#define FUSE_BASE__INST1_SEG0 0 +#define FUSE_BASE__INST1_SEG1 0 +#define FUSE_BASE__INST1_SEG2 0 +#define FUSE_BASE__INST1_SEG3 0 +#define FUSE_BASE__INST1_SEG4 0 + +#define FUSE_BASE__INST2_SEG0 0 +#define FUSE_BASE__INST2_SEG1 0 +#define FUSE_BASE__INST2_SEG2 0 +#define FUSE_BASE__INST2_SEG3 0 +#define FUSE_BASE__INST2_SEG4 0 + +#define FUSE_BASE__INST3_SEG0 0 +#define FUSE_BASE__INST3_SEG1 0 +#define FUSE_BASE__INST3_SEG2 0 +#define FUSE_BASE__INST3_SEG3 0 +#define FUSE_BASE__INST3_SEG4 0 + +#define FUSE_BASE__INST4_SEG0 0 +#define FUSE_BASE__INST4_SEG1 0 +#define FUSE_BASE__INST4_SEG2 0 +#define FUSE_BASE__INST4_SEG3 0 +#define FUSE_BASE__INST4_SEG4 0 + +#define FUSE_BASE__INST5_SEG0 0 +#define FUSE_BASE__INST5_SEG1 0 +#define FUSE_BASE__INST5_SEG2 0 +#define FUSE_BASE__INST5_SEG3 0 +#define FUSE_BASE__INST5_SEG4 0 + +#define FUSE_BASE__INST6_SEG0 0 +#define FUSE_BASE__INST6_SEG1 0 +#define FUSE_BASE__INST6_SEG2 0 +#define FUSE_BASE__INST6_SEG3 0 +#define FUSE_BASE__INST6_SEG4 0 + +#define GC_BASE__INST0_SEG0 0x00001260 +#define GC_BASE__INST0_SEG1 0x0000A000 +#define GC_BASE__INST0_SEG2 0x02402C00 +#define GC_BASE__INST0_SEG3 0 +#define GC_BASE__INST0_SEG4 0 + +#define GC_BASE__INST1_SEG0 0 +#define GC_BASE__INST1_SEG1 0 +#define GC_BASE__INST1_SEG2 0 +#define GC_BASE__INST1_SEG3 0 +#define GC_BASE__INST1_SEG4 0 + +#define GC_BASE__INST2_SEG0 0 +#define GC_BASE__INST2_SEG1 0 +#define GC_BASE__INST2_SEG2 0 +#define GC_BASE__INST2_SEG3 0 +#define GC_BASE__INST2_SEG4 0 + +#define GC_BASE__INST3_SEG0 0 +#define GC_BASE__INST3_SEG1 0 +#define GC_BASE__INST3_SEG2 0 +#define GC_BASE__INST3_SEG3 0 +#define GC_BASE__INST3_SEG4 0 + +#define GC_BASE__INST4_SEG0 0 +#define GC_BASE__INST4_SEG1 0 +#define GC_BASE__INST4_SEG2 0 +#define GC_BASE__INST4_SEG3 0 +#define GC_BASE__INST4_SEG4 0 + +#define GC_BASE__INST5_SEG0 0 +#define GC_BASE__INST5_SEG1 0 +#define GC_BASE__INST5_SEG2 0 +#define GC_BASE__INST5_SEG3 0 +#define GC_BASE__INST5_SEG4 0 + +#define GC_BASE__INST6_SEG0 0 +#define GC_BASE__INST6_SEG1 0 +#define GC_BASE__INST6_SEG2 0 +#define GC_BASE__INST6_SEG3 0 +#define GC_BASE__INST6_SEG4 0 + +#define HDA_BASE__INST0_SEG0 0x004C0000 +#define HDA_BASE__INST0_SEG1 0x02404800 +#define HDA_BASE__INST0_SEG2 0 +#define HDA_BASE__INST0_SEG3 0 +#define HDA_BASE__INST0_SEG4 0 + +#define HDA_BASE__INST1_SEG0 0 +#define HDA_BASE__INST1_SEG1 0 +#define HDA_BASE__INST1_SEG2 0 +#define HDA_BASE__INST1_SEG3 0 +#define HDA_BASE__INST1_SEG4 0 + +#define HDA_BASE__INST2_SEG0 0 +#define HDA_BASE__INST2_SEG1 0 +#define HDA_BASE__INST2_SEG2 0 +#define HDA_BASE__INST2_SEG3 0 +#define HDA_BASE__INST2_SEG4 0 + +#define HDA_BASE__INST3_SEG0 0 +#define HDA_BASE__INST3_SEG1 0 +#define HDA_BASE__INST3_SEG2 0 +#define HDA_BASE__INST3_SEG3 0 +#define HDA_BASE__INST3_SEG4 0 + +#define HDA_BASE__INST4_SEG0 0 +#define HDA_BASE__INST4_SEG1 0 +#define HDA_BASE__INST4_SEG2 0 +#define HDA_BASE__INST4_SEG3 0 +#define HDA_BASE__INST4_SEG4 0 + +#define HDA_BASE__INST5_SEG0 0 +#define HDA_BASE__INST5_SEG1 0 +#define HDA_BASE__INST5_SEG2 0 +#define HDA_BASE__INST5_SEG3 0 +#define HDA_BASE__INST5_SEG4 0 + +#define HDA_BASE__INST6_SEG0 0 +#define HDA_BASE__INST6_SEG1 0 +#define HDA_BASE__INST6_SEG2 0 +#define HDA_BASE__INST6_SEG3 0 +#define HDA_BASE__INST6_SEG4 0 + +#define HDP_BASE__INST0_SEG0 0x00000F20 +#define HDP_BASE__INST0_SEG1 0x0240A400 +#define HDP_BASE__INST0_SEG2 0 +#define HDP_BASE__INST0_SEG3 0 +#define HDP_BASE__INST0_SEG4 0 + +#define HDP_BASE__INST1_SEG0 0 +#define HDP_BASE__INST1_SEG1 0 +#define HDP_BASE__INST1_SEG2 0 +#define HDP_BASE__INST1_SEG3 0 +#define HDP_BASE__INST1_SEG4 0 + +#define HDP_BASE__INST2_SEG0 0 +#define HDP_BASE__INST2_SEG1 0 +#define HDP_BASE__INST2_SEG2 0 +#define HDP_BASE__INST2_SEG3 0 +#define HDP_BASE__INST2_SEG4 0 + +#define HDP_BASE__INST3_SEG0 0 +#define HDP_BASE__INST3_SEG1 0 +#define HDP_BASE__INST3_SEG2 0 +#define HDP_BASE__INST3_SEG3 0 +#define HDP_BASE__INST3_SEG4 0 + +#define HDP_BASE__INST4_SEG0 0 +#define HDP_BASE__INST4_SEG1 0 +#define HDP_BASE__INST4_SEG2 0 +#define HDP_BASE__INST4_SEG3 0 +#define HDP_BASE__INST4_SEG4 0 + +#define HDP_BASE__INST5_SEG0 0 +#define HDP_BASE__INST5_SEG1 0 +#define HDP_BASE__INST5_SEG2 0 +#define HDP_BASE__INST5_SEG3 0 +#define HDP_BASE__INST5_SEG4 0 + +#define HDP_BASE__INST6_SEG0 0 +#define HDP_BASE__INST6_SEG1 0 +#define HDP_BASE__INST6_SEG2 0 +#define HDP_BASE__INST6_SEG3 0 +#define HDP_BASE__INST6_SEG4 0 + +#define MMHUB_BASE__INST0_SEG0 0x0001A000 +#define MMHUB_BASE__INST0_SEG1 0x02408800 +#define MMHUB_BASE__INST0_SEG2 0 +#define MMHUB_BASE__INST0_SEG3 0 +#define MMHUB_BASE__INST0_SEG4 0 + +#define MMHUB_BASE__INST1_SEG0 0 +#define MMHUB_BASE__INST1_SEG1 0 +#define MMHUB_BASE__INST1_SEG2 0 +#define MMHUB_BASE__INST1_SEG3 0 +#define MMHUB_BASE__INST1_SEG4 0 + +#define MMHUB_BASE__INST2_SEG0 0 +#define MMHUB_BASE__INST2_SEG1 0 +#define MMHUB_BASE__INST2_SEG2 0 +#define MMHUB_BASE__INST2_SEG3 0 +#define MMHUB_BASE__INST2_SEG4 0 + +#define MMHUB_BASE__INST3_SEG0 0 +#define MMHUB_BASE__INST3_SEG1 0 +#define MMHUB_BASE__INST3_SEG2 0 +#define MMHUB_BASE__INST3_SEG3 0 +#define MMHUB_BASE__INST3_SEG4 0 + +#define MMHUB_BASE__INST4_SEG0 0 +#define MMHUB_BASE__INST4_SEG1 0 +#define MMHUB_BASE__INST4_SEG2 0 +#define MMHUB_BASE__INST4_SEG3 0 +#define MMHUB_BASE__INST4_SEG4 0 + +#define MMHUB_BASE__INST5_SEG0 0 +#define MMHUB_BASE__INST5_SEG1 0 +#define MMHUB_BASE__INST5_SEG2 0 +#define MMHUB_BASE__INST5_SEG3 0 +#define MMHUB_BASE__INST5_SEG4 0 + +#define MMHUB_BASE__INST6_SEG0 0 +#define MMHUB_BASE__INST6_SEG1 0 +#define MMHUB_BASE__INST6_SEG2 0 +#define MMHUB_BASE__INST6_SEG3 0 +#define MMHUB_BASE__INST6_SEG4 0 + +#define MP0_BASE__INST0_SEG0 0x00016000 +#define MP0_BASE__INST0_SEG1 0x00DC0000 +#define MP0_BASE__INST0_SEG2 0x00E00000 +#define MP0_BASE__INST0_SEG3 0x00E40000 +#define MP0_BASE__INST0_SEG4 0x0243FC00 + +#define MP0_BASE__INST1_SEG0 0 +#define MP0_BASE__INST1_SEG1 0 +#define MP0_BASE__INST1_SEG2 0 +#define MP0_BASE__INST1_SEG3 0 +#define MP0_BASE__INST1_SEG4 0 + +#define MP0_BASE__INST2_SEG0 0 +#define MP0_BASE__INST2_SEG1 0 +#define MP0_BASE__INST2_SEG2 0 +#define MP0_BASE__INST2_SEG3 0 +#define MP0_BASE__INST2_SEG4 0 + +#define MP0_BASE__INST3_SEG0 0 +#define MP0_BASE__INST3_SEG1 0 +#define MP0_BASE__INST3_SEG2 0 +#define MP0_BASE__INST3_SEG3 0 +#define MP0_BASE__INST3_SEG4 0 + +#define MP0_BASE__INST4_SEG0 0 +#define MP0_BASE__INST4_SEG1 0 +#define MP0_BASE__INST4_SEG2 0 +#define MP0_BASE__INST4_SEG3 0 +#define MP0_BASE__INST4_SEG4 0 + +#define MP0_BASE__INST5_SEG0 0 +#define MP0_BASE__INST5_SEG1 0 +#define MP0_BASE__INST5_SEG2 0 +#define MP0_BASE__INST5_SEG3 0 +#define MP0_BASE__INST5_SEG4 0 + +#define MP0_BASE__INST6_SEG0 0 +#define MP0_BASE__INST6_SEG1 0 +#define MP0_BASE__INST6_SEG2 0 +#define MP0_BASE__INST6_SEG3 0 +#define MP0_BASE__INST6_SEG4 0 + +#define MP1_BASE__INST0_SEG0 0x00016200 +#define MP1_BASE__INST0_SEG1 0x00E80000 +#define MP1_BASE__INST0_SEG2 0x00EC0000 +#define MP1_BASE__INST0_SEG3 0x00F00000 +#define MP1_BASE__INST0_SEG4 0x02400400 + +#define MP1_BASE__INST1_SEG0 0 +#define MP1_BASE__INST1_SEG1 0 +#define MP1_BASE__INST1_SEG2 0 +#define MP1_BASE__INST1_SEG3 0 +#define MP1_BASE__INST1_SEG4 0 + +#define MP1_BASE__INST2_SEG0 0 +#define MP1_BASE__INST2_SEG1 0 +#define MP1_BASE__INST2_SEG2 0 +#define MP1_BASE__INST2_SEG3 0 +#define MP1_BASE__INST2_SEG4 0 + +#define MP1_BASE__INST3_SEG0 0 +#define MP1_BASE__INST3_SEG1 0 +#define MP1_BASE__INST3_SEG2 0 +#define MP1_BASE__INST3_SEG3 0 +#define MP1_BASE__INST3_SEG4 0 + +#define MP1_BASE__INST4_SEG0 0 +#define MP1_BASE__INST4_SEG1 0 +#define MP1_BASE__INST4_SEG2 0 +#define MP1_BASE__INST4_SEG3 0 +#define MP1_BASE__INST4_SEG4 0 + +#define MP1_BASE__INST5_SEG0 0 +#define MP1_BASE__INST5_SEG1 0 +#define MP1_BASE__INST5_SEG2 0 +#define MP1_BASE__INST5_SEG3 0 +#define MP1_BASE__INST5_SEG4 0 + +#define MP1_BASE__INST6_SEG0 0 +#define MP1_BASE__INST6_SEG1 0 +#define MP1_BASE__INST6_SEG2 0 +#define MP1_BASE__INST6_SEG3 0 +#define MP1_BASE__INST6_SEG4 0 + +#define NBIF0_BASE__INST0_SEG0 0x00000000 +#define NBIF0_BASE__INST0_SEG1 0x00000014 +#define NBIF0_BASE__INST0_SEG2 0x00000D20 +#define NBIF0_BASE__INST0_SEG3 0x00010400 +#define NBIF0_BASE__INST0_SEG4 0x0241B000 + +#define NBIF0_BASE__INST1_SEG0 0 +#define NBIF0_BASE__INST1_SEG1 0 +#define NBIF0_BASE__INST1_SEG2 0 +#define NBIF0_BASE__INST1_SEG3 0 +#define NBIF0_BASE__INST1_SEG4 0 + +#define NBIF0_BASE__INST2_SEG0 0 +#define NBIF0_BASE__INST2_SEG1 0 +#define NBIF0_BASE__INST2_SEG2 0 +#define NBIF0_BASE__INST2_SEG3 0 +#define NBIF0_BASE__INST2_SEG4 0 + +#define NBIF0_BASE__INST3_SEG0 0 +#define NBIF0_BASE__INST3_SEG1 0 +#define NBIF0_BASE__INST3_SEG2 0 +#define NBIF0_BASE__INST3_SEG3 0 +#define NBIF0_BASE__INST3_SEG4 0 + +#define NBIF0_BASE__INST4_SEG0 0 +#define NBIF0_BASE__INST4_SEG1 0 +#define NBIF0_BASE__INST4_SEG2 0 +#define NBIF0_BASE__INST4_SEG3 0 +#define NBIF0_BASE__INST4_SEG4 0 + +#define NBIF0_BASE__INST5_SEG0 0 +#define NBIF0_BASE__INST5_SEG1 0 +#define NBIF0_BASE__INST5_SEG2 0 +#define NBIF0_BASE__INST5_SEG3 0 +#define NBIF0_BASE__INST5_SEG4 0 + +#define NBIF0_BASE__INST6_SEG0 0 +#define NBIF0_BASE__INST6_SEG1 0 +#define NBIF0_BASE__INST6_SEG2 0 +#define NBIF0_BASE__INST6_SEG3 0 +#define NBIF0_BASE__INST6_SEG4 0 + +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 +#define OSSSYS_BASE__INST0_SEG1 0x0240A000 +#define OSSSYS_BASE__INST0_SEG2 0 +#define OSSSYS_BASE__INST0_SEG3 0 +#define OSSSYS_BASE__INST0_SEG4 0 + +#define OSSSYS_BASE__INST1_SEG0 0 +#define OSSSYS_BASE__INST1_SEG1 0 +#define OSSSYS_BASE__INST1_SEG2 0 +#define OSSSYS_BASE__INST1_SEG3 0 +#define OSSSYS_BASE__INST1_SEG4 0 + +#define OSSSYS_BASE__INST2_SEG0 0 +#define OSSSYS_BASE__INST2_SEG1 0 +#define OSSSYS_BASE__INST2_SEG2 0 +#define OSSSYS_BASE__INST2_SEG3 0 +#define OSSSYS_BASE__INST2_SEG4 0 + +#define OSSSYS_BASE__INST3_SEG0 0 +#define OSSSYS_BASE__INST3_SEG1 0 +#define OSSSYS_BASE__INST3_SEG2 0 +#define OSSSYS_BASE__INST3_SEG3 0 +#define OSSSYS_BASE__INST3_SEG4 0 + +#define OSSSYS_BASE__INST4_SEG0 0 +#define OSSSYS_BASE__INST4_SEG1 0 +#define OSSSYS_BASE__INST4_SEG2 0 +#define OSSSYS_BASE__INST4_SEG3 0 +#define OSSSYS_BASE__INST4_SEG4 0 + +#define OSSSYS_BASE__INST5_SEG0 0 +#define OSSSYS_BASE__INST5_SEG1 0 +#define OSSSYS_BASE__INST5_SEG2 0 +#define OSSSYS_BASE__INST5_SEG3 0 +#define OSSSYS_BASE__INST5_SEG4 0 + +#define OSSSYS_BASE__INST6_SEG0 0 +#define OSSSYS_BASE__INST6_SEG1 0 +#define OSSSYS_BASE__INST6_SEG2 0 +#define OSSSYS_BASE__INST6_SEG3 0 +#define OSSSYS_BASE__INST6_SEG4 0 + +#define PCIE0_BASE__INST0_SEG0 0x02411800 +#define PCIE0_BASE__INST0_SEG1 0x04440000 +#define PCIE0_BASE__INST0_SEG2 0 +#define PCIE0_BASE__INST0_SEG3 0 +#define PCIE0_BASE__INST0_SEG4 0 + +#define PCIE0_BASE__INST1_SEG0 0 +#define PCIE0_BASE__INST1_SEG1 0 +#define PCIE0_BASE__INST1_SEG2 0 +#define PCIE0_BASE__INST1_SEG3 0 +#define PCIE0_BASE__INST1_SEG4 0 + +#define PCIE0_BASE__INST2_SEG0 0 +#define PCIE0_BASE__INST2_SEG1 0 +#define PCIE0_BASE__INST2_SEG2 0 +#define PCIE0_BASE__INST2_SEG3 0 +#define PCIE0_BASE__INST2_SEG4 0 + +#define PCIE0_BASE__INST3_SEG0 0 +#define PCIE0_BASE__INST3_SEG1 0 +#define PCIE0_BASE__INST3_SEG2 0 +#define PCIE0_BASE__INST3_SEG3 0 +#define PCIE0_BASE__INST3_SEG4 0 + +#define PCIE0_BASE__INST4_SEG0 0 +#define PCIE0_BASE__INST4_SEG1 0 +#define PCIE0_BASE__INST4_SEG2 0 +#define PCIE0_BASE__INST4_SEG3 0 +#define PCIE0_BASE__INST4_SEG4 0 + +#define PCIE0_BASE__INST5_SEG0 0 +#define PCIE0_BASE__INST5_SEG1 0 +#define PCIE0_BASE__INST5_SEG2 0 +#define PCIE0_BASE__INST5_SEG3 0 +#define PCIE0_BASE__INST5_SEG4 0 + +#define PCIE0_BASE__INST6_SEG0 0 +#define PCIE0_BASE__INST6_SEG1 0 +#define PCIE0_BASE__INST6_SEG2 0 +#define PCIE0_BASE__INST6_SEG3 0 +#define PCIE0_BASE__INST6_SEG4 0 + +#define SDMA_BASE__INST0_SEG0 0x00001260 +#define SDMA_BASE__INST0_SEG1 0x0000A000 +#define SDMA_BASE__INST0_SEG2 0x02402C00 +#define SDMA_BASE__INST0_SEG3 0 +#define SDMA_BASE__INST0_SEG4 0 + +#define SDMA_BASE__INST1_SEG0 0x00001260 +#define SDMA_BASE__INST1_SEG1 0x0000A000 +#define SDMA_BASE__INST1_SEG2 0x02402C00 +#define SDMA_BASE__INST1_SEG3 0 +#define SDMA_BASE__INST1_SEG4 0 + +#define SDMA_BASE__INST2_SEG0 0 +#define SDMA_BASE__INST2_SEG1 0 +#define SDMA_BASE__INST2_SEG2 0 +#define SDMA_BASE__INST2_SEG3 0 +#define SDMA_BASE__INST2_SEG4 0 + +#define SDMA_BASE__INST3_SEG0 0 +#define SDMA_BASE__INST3_SEG1 0 +#define SDMA_BASE__INST3_SEG2 0 +#define SDMA_BASE__INST3_SEG3 0 +#define SDMA_BASE__INST3_SEG4 0 + +#define SDMA_BASE__INST4_SEG0 0 +#define SDMA_BASE__INST4_SEG1 0 +#define SDMA_BASE__INST4_SEG2 0 +#define SDMA_BASE__INST4_SEG3 0 +#define SDMA_BASE__INST4_SEG4 0 + +#define SDMA_BASE__INST5_SEG0 0 +#define SDMA_BASE__INST5_SEG1 0 +#define SDMA_BASE__INST5_SEG2 0 +#define SDMA_BASE__INST5_SEG3 0 +#define SDMA_BASE__INST5_SEG4 0 + +#define SDMA_BASE__INST6_SEG0 0 +#define SDMA_BASE__INST6_SEG1 0 +#define SDMA_BASE__INST6_SEG2 0 +#define SDMA_BASE__INST6_SEG3 0 +#define SDMA_BASE__INST6_SEG4 0 + +#define SMUIO_BASE__INST0_SEG0 0x00016800 +#define SMUIO_BASE__INST0_SEG1 0x00016A00 +#define SMUIO_BASE__INST0_SEG2 0x00440000 +#define SMUIO_BASE__INST0_SEG3 0x02401000 +#define SMUIO_BASE__INST0_SEG4 0 + +#define SMUIO_BASE__INST1_SEG0 0 +#define SMUIO_BASE__INST1_SEG1 0 +#define SMUIO_BASE__INST1_SEG2 0 +#define SMUIO_BASE__INST1_SEG3 0 +#define SMUIO_BASE__INST1_SEG4 0 + +#define SMUIO_BASE__INST2_SEG0 0 +#define SMUIO_BASE__INST2_SEG1 0 +#define SMUIO_BASE__INST2_SEG2 0 +#define SMUIO_BASE__INST2_SEG3 0 +#define SMUIO_BASE__INST2_SEG4 0 + +#define SMUIO_BASE__INST3_SEG0 0 +#define SMUIO_BASE__INST3_SEG1 0 +#define SMUIO_BASE__INST3_SEG2 0 +#define SMUIO_BASE__INST3_SEG3 0 +#define SMUIO_BASE__INST3_SEG4 0 + +#define SMUIO_BASE__INST4_SEG0 0 +#define SMUIO_BASE__INST4_SEG1 0 +#define SMUIO_BASE__INST4_SEG2 0 +#define SMUIO_BASE__INST4_SEG3 0 +#define SMUIO_BASE__INST4_SEG4 0 + +#define SMUIO_BASE__INST5_SEG0 0 +#define SMUIO_BASE__INST5_SEG1 0 +#define SMUIO_BASE__INST5_SEG2 0 +#define SMUIO_BASE__INST5_SEG3 0 +#define SMUIO_BASE__INST5_SEG4 0 + +#define SMUIO_BASE__INST6_SEG0 0 +#define SMUIO_BASE__INST6_SEG1 0 +#define SMUIO_BASE__INST6_SEG2 0 +#define SMUIO_BASE__INST6_SEG3 0 +#define SMUIO_BASE__INST6_SEG4 0 + +#define THM_BASE__INST0_SEG0 0x00016600 +#define THM_BASE__INST0_SEG1 0x02400C00 +#define THM_BASE__INST0_SEG2 0 +#define THM_BASE__INST0_SEG3 0 +#define THM_BASE__INST0_SEG4 0 + +#define THM_BASE__INST1_SEG0 0 +#define THM_BASE__INST1_SEG1 0 +#define THM_BASE__INST1_SEG2 0 +#define THM_BASE__INST1_SEG3 0 +#define THM_BASE__INST1_SEG4 0 + +#define THM_BASE__INST2_SEG0 0 +#define THM_BASE__INST2_SEG1 0 +#define THM_BASE__INST2_SEG2 0 +#define THM_BASE__INST2_SEG3 0 +#define THM_BASE__INST2_SEG4 0 + +#define THM_BASE__INST3_SEG0 0 +#define THM_BASE__INST3_SEG1 0 +#define THM_BASE__INST3_SEG2 0 +#define THM_BASE__INST3_SEG3 0 +#define THM_BASE__INST3_SEG4 0 + +#define THM_BASE__INST4_SEG0 0 +#define THM_BASE__INST4_SEG1 0 +#define THM_BASE__INST4_SEG2 0 +#define THM_BASE__INST4_SEG3 0 +#define THM_BASE__INST4_SEG4 0 + +#define THM_BASE__INST5_SEG0 0 +#define THM_BASE__INST5_SEG1 0 +#define THM_BASE__INST5_SEG2 0 +#define THM_BASE__INST5_SEG3 0 +#define THM_BASE__INST5_SEG4 0 + +#define THM_BASE__INST6_SEG0 0 +#define THM_BASE__INST6_SEG1 0 +#define THM_BASE__INST6_SEG2 0 +#define THM_BASE__INST6_SEG3 0 +#define THM_BASE__INST6_SEG4 0 + +#define UMC_BASE__INST0_SEG0 0x00014000 +#define UMC_BASE__INST0_SEG1 0x02425800 +#define UMC_BASE__INST0_SEG2 0 +#define UMC_BASE__INST0_SEG3 0 +#define UMC_BASE__INST0_SEG4 0 + +#define UMC_BASE__INST1_SEG0 0x00054000 +#define UMC_BASE__INST1_SEG1 0x02425C00 +#define UMC_BASE__INST1_SEG2 0 +#define UMC_BASE__INST1_SEG3 0 +#define UMC_BASE__INST1_SEG4 0 + +#define UMC_BASE__INST2_SEG0 0x00094000 +#define UMC_BASE__INST2_SEG1 0x02426000 +#define UMC_BASE__INST2_SEG2 0 +#define UMC_BASE__INST2_SEG3 0 +#define UMC_BASE__INST2_SEG4 0 + +#define UMC_BASE__INST3_SEG0 0x000D4000 +#define UMC_BASE__INST3_SEG1 0x02426400 +#define UMC_BASE__INST3_SEG2 0 +#define UMC_BASE__INST3_SEG3 0 +#define UMC_BASE__INST3_SEG4 0 + +#define UMC_BASE__INST4_SEG0 0 +#define UMC_BASE__INST4_SEG1 0 +#define UMC_BASE__INST4_SEG2 0 +#define UMC_BASE__INST4_SEG3 0 +#define UMC_BASE__INST4_SEG4 0 + +#define UMC_BASE__INST5_SEG0 0 +#define UMC_BASE__INST5_SEG1 0 +#define UMC_BASE__INST5_SEG2 0 +#define UMC_BASE__INST5_SEG3 0 +#define UMC_BASE__INST5_SEG4 0 + +#define UMC_BASE__INST6_SEG0 0 +#define UMC_BASE__INST6_SEG1 0 +#define UMC_BASE__INST6_SEG2 0 +#define UMC_BASE__INST6_SEG3 0 +#define UMC_BASE__INST6_SEG4 0 + +#define USB0_BASE__INST0_SEG0 0x0242A800 +#define USB0_BASE__INST0_SEG1 0x05B00000 +#define USB0_BASE__INST0_SEG2 0 +#define USB0_BASE__INST0_SEG3 0 +#define USB0_BASE__INST0_SEG4 0 + +#define USB0_BASE__INST1_SEG0 0 +#define USB0_BASE__INST1_SEG1 0 +#define USB0_BASE__INST1_SEG2 0 +#define USB0_BASE__INST1_SEG3 0 +#define USB0_BASE__INST1_SEG4 0 + +#define USB0_BASE__INST2_SEG0 0 +#define USB0_BASE__INST2_SEG1 0 +#define USB0_BASE__INST2_SEG2 0 +#define USB0_BASE__INST2_SEG3 0 +#define USB0_BASE__INST2_SEG4 0 + +#define USB0_BASE__INST3_SEG0 0 +#define USB0_BASE__INST3_SEG1 0 +#define USB0_BASE__INST3_SEG2 0 +#define USB0_BASE__INST3_SEG3 0 +#define USB0_BASE__INST3_SEG4 0 + +#define USB0_BASE__INST4_SEG0 0 +#define USB0_BASE__INST4_SEG1 0 +#define USB0_BASE__INST4_SEG2 0 +#define USB0_BASE__INST4_SEG3 0 +#define USB0_BASE__INST4_SEG4 0 + +#define USB0_BASE__INST5_SEG0 0 +#define USB0_BASE__INST5_SEG1 0 +#define USB0_BASE__INST5_SEG2 0 +#define USB0_BASE__INST5_SEG3 0 +#define USB0_BASE__INST5_SEG4 0 + +#define USB0_BASE__INST6_SEG0 0 +#define USB0_BASE__INST6_SEG1 0 +#define USB0_BASE__INST6_SEG2 0 +#define USB0_BASE__INST6_SEG3 0 +#define USB0_BASE__INST6_SEG4 0 + +#define UVD0_BASE__INST0_SEG0 0x00007800 +#define UVD0_BASE__INST0_SEG1 0x00007E00 +#define UVD0_BASE__INST0_SEG2 0x02403000 +#define UVD0_BASE__INST0_SEG3 0 +#define UVD0_BASE__INST0_SEG4 0 + +#define UVD0_BASE__INST1_SEG0 0 +#define UVD0_BASE__INST1_SEG1 0 +#define UVD0_BASE__INST1_SEG2 0 +#define UVD0_BASE__INST1_SEG3 0 +#define UVD0_BASE__INST1_SEG4 0 + +#define UVD0_BASE__INST2_SEG0 0 +#define UVD0_BASE__INST2_SEG1 0 +#define UVD0_BASE__INST2_SEG2 0 +#define UVD0_BASE__INST2_SEG3 0 +#define UVD0_BASE__INST2_SEG4 0 + +#define UVD0_BASE__INST3_SEG0 0 +#define UVD0_BASE__INST3_SEG1 0 +#define UVD0_BASE__INST3_SEG2 0 +#define UVD0_BASE__INST3_SEG3 0 +#define UVD0_BASE__INST3_SEG4 0 + +#define UVD0_BASE__INST4_SEG0 0 +#define UVD0_BASE__INST4_SEG1 0 +#define UVD0_BASE__INST4_SEG2 0 +#define UVD0_BASE__INST4_SEG3 0 +#define UVD0_BASE__INST4_SEG4 0 + +#define UVD0_BASE__INST5_SEG0 0 +#define UVD0_BASE__INST5_SEG1 0 +#define UVD0_BASE__INST5_SEG2 0 +#define UVD0_BASE__INST5_SEG3 0 +#define UVD0_BASE__INST5_SEG4 0 + +#define UVD0_BASE__INST6_SEG0 0 +#define UVD0_BASE__INST6_SEG1 0 +#define UVD0_BASE__INST6_SEG2 0 +#define UVD0_BASE__INST6_SEG3 0 +#define UVD0_BASE__INST6_SEG4 0 + +#endif diff --git a/src/amd/amdgpu/include/navi14_ip_offset.h b/src/amd/amdgpu/include/navi14_ip_offset.h new file mode 100644 index 0000000..47ce105 --- /dev/null +++ b/src/amd/amdgpu/include/navi14_ip_offset.h @@ -0,0 +1,1116 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _navi14_ip_offset_HEADER +#define _navi14_ip_offset_HEADER + +#define MAX_INSTANCE 7 +#define MAX_SEGMENT 5 + +struct IP_BASE_INSTANCE +{ + unsigned int segment[MAX_SEGMENT]; +}; + +struct IP_BASE +{ + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; +}; + +static const struct IP_BASE ATHUB_BASE = {{{{0x00000C00, 0x02408C00, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE CLK_BASE = {{{{0x00016C00, 0x02401800, 0, 0, 0}}, + {{0x00016E00, 0x02401C00, 0, 0, 0}}, + {{0x00017000, 0x02402000, 0, 0, 0}}, + {{0x00017200, 0x02402400, 0, 0, 0}}, + {{0x0001B000, 0x0242D800, 0, 0, 0}}, + {{0x00017E00, 0x0240BC00, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE DF_BASE = {{{{0x00007000, 0x0240B800, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE DIO_BASE = {{{{0x02404000, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE DMU_BASE = {{{{0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE DPCS_BASE = {{{{0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE FUSE_BASE = {{{{0x00017400, 0x02401400, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE GC_BASE = {{{{0x00001260, 0x0000A000, 0x02402C00, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE HDA_BASE = {{{{0x004C0000, 0x02404800, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE HDP_BASE = {{{{0x00000F20, 0x0240A400, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE MMHUB_BASE = {{{{0x0001A000, 0x02408800, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE MP0_BASE = {{{{0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE MP1_BASE = {{{{0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE NBIF0_BASE = {{{{0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE OSSSYS_BASE = {{{{0x000010A0, 0x0240A000, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE PCIE0_BASE = {{{{0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE SDMA_BASE = {{{{0x00001260, 0x0000A000, 0x02402C00, 0, 0}}, + {{0x00001260, 0x0000A000, 0x02402C00, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE SMUIO_BASE = {{{{0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE THM_BASE = {{{{0x00016600, 0x02400C00, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE UMC_BASE = {{{{0x00014000, 0x02425800, 0, 0, 0}}, + {{0x00054000, 0x02425C00, 0, 0, 0}}, + {{0x00094000, 0x02426000, 0, 0, 0}}, + {{0x000D4000, 0x02426400, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE USB0_BASE = {{{{0x0242A800, 0x05B00000, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE UVD0_BASE = {{{{0x00007800, 0x00007E00, 0x02403000, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; + +#define ATHUB_BASE__INST0_SEG0 0x00000C00 +#define ATHUB_BASE__INST0_SEG1 0x02408C00 +#define ATHUB_BASE__INST0_SEG2 0 +#define ATHUB_BASE__INST0_SEG3 0 +#define ATHUB_BASE__INST0_SEG4 0 + +#define ATHUB_BASE__INST1_SEG0 0 +#define ATHUB_BASE__INST1_SEG1 0 +#define ATHUB_BASE__INST1_SEG2 0 +#define ATHUB_BASE__INST1_SEG3 0 +#define ATHUB_BASE__INST1_SEG4 0 + +#define ATHUB_BASE__INST2_SEG0 0 +#define ATHUB_BASE__INST2_SEG1 0 +#define ATHUB_BASE__INST2_SEG2 0 +#define ATHUB_BASE__INST2_SEG3 0 +#define ATHUB_BASE__INST2_SEG4 0 + +#define ATHUB_BASE__INST3_SEG0 0 +#define ATHUB_BASE__INST3_SEG1 0 +#define ATHUB_BASE__INST3_SEG2 0 +#define ATHUB_BASE__INST3_SEG3 0 +#define ATHUB_BASE__INST3_SEG4 0 + +#define ATHUB_BASE__INST4_SEG0 0 +#define ATHUB_BASE__INST4_SEG1 0 +#define ATHUB_BASE__INST4_SEG2 0 +#define ATHUB_BASE__INST4_SEG3 0 +#define ATHUB_BASE__INST4_SEG4 0 + +#define ATHUB_BASE__INST5_SEG0 0 +#define ATHUB_BASE__INST5_SEG1 0 +#define ATHUB_BASE__INST5_SEG2 0 +#define ATHUB_BASE__INST5_SEG3 0 +#define ATHUB_BASE__INST5_SEG4 0 + +#define ATHUB_BASE__INST6_SEG0 0 +#define ATHUB_BASE__INST6_SEG1 0 +#define ATHUB_BASE__INST6_SEG2 0 +#define ATHUB_BASE__INST6_SEG3 0 +#define ATHUB_BASE__INST6_SEG4 0 + +#define CLK_BASE__INST0_SEG0 0x00016C00 +#define CLK_BASE__INST0_SEG1 0x02401800 +#define CLK_BASE__INST0_SEG2 0 +#define CLK_BASE__INST0_SEG3 0 +#define CLK_BASE__INST0_SEG4 0 + +#define CLK_BASE__INST1_SEG0 0x00016E00 +#define CLK_BASE__INST1_SEG1 0x02401C00 +#define CLK_BASE__INST1_SEG2 0 +#define CLK_BASE__INST1_SEG3 0 +#define CLK_BASE__INST1_SEG4 0 + +#define CLK_BASE__INST2_SEG0 0x00017000 +#define CLK_BASE__INST2_SEG1 0x02402000 +#define CLK_BASE__INST2_SEG2 0 +#define CLK_BASE__INST2_SEG3 0 +#define CLK_BASE__INST2_SEG4 0 + +#define CLK_BASE__INST3_SEG0 0x00017200 +#define CLK_BASE__INST3_SEG1 0x02402400 +#define CLK_BASE__INST3_SEG2 0 +#define CLK_BASE__INST3_SEG3 0 +#define CLK_BASE__INST3_SEG4 0 + +#define CLK_BASE__INST4_SEG0 0x0001B000 +#define CLK_BASE__INST4_SEG1 0x0242D800 +#define CLK_BASE__INST4_SEG2 0 +#define CLK_BASE__INST4_SEG3 0 +#define CLK_BASE__INST4_SEG4 0 + +#define CLK_BASE__INST5_SEG0 0x00017E00 +#define CLK_BASE__INST5_SEG1 0x0240BC00 +#define CLK_BASE__INST5_SEG2 0 +#define CLK_BASE__INST5_SEG3 0 +#define CLK_BASE__INST5_SEG4 0 + +#define CLK_BASE__INST6_SEG0 0 +#define CLK_BASE__INST6_SEG1 0 +#define CLK_BASE__INST6_SEG2 0 +#define CLK_BASE__INST6_SEG3 0 +#define CLK_BASE__INST6_SEG4 0 + +#define DF_BASE__INST0_SEG0 0x00007000 +#define DF_BASE__INST0_SEG1 0x0240B800 +#define DF_BASE__INST0_SEG2 0 +#define DF_BASE__INST0_SEG3 0 +#define DF_BASE__INST0_SEG4 0 + +#define DF_BASE__INST1_SEG0 0 +#define DF_BASE__INST1_SEG1 0 +#define DF_BASE__INST1_SEG2 0 +#define DF_BASE__INST1_SEG3 0 +#define DF_BASE__INST1_SEG4 0 + +#define DF_BASE__INST2_SEG0 0 +#define DF_BASE__INST2_SEG1 0 +#define DF_BASE__INST2_SEG2 0 +#define DF_BASE__INST2_SEG3 0 +#define DF_BASE__INST2_SEG4 0 + +#define DF_BASE__INST3_SEG0 0 +#define DF_BASE__INST3_SEG1 0 +#define DF_BASE__INST3_SEG2 0 +#define DF_BASE__INST3_SEG3 0 +#define DF_BASE__INST3_SEG4 0 + +#define DF_BASE__INST4_SEG0 0 +#define DF_BASE__INST4_SEG1 0 +#define DF_BASE__INST4_SEG2 0 +#define DF_BASE__INST4_SEG3 0 +#define DF_BASE__INST4_SEG4 0 + +#define DF_BASE__INST5_SEG0 0 +#define DF_BASE__INST5_SEG1 0 +#define DF_BASE__INST5_SEG2 0 +#define DF_BASE__INST5_SEG3 0 +#define DF_BASE__INST5_SEG4 0 + +#define DF_BASE__INST6_SEG0 0 +#define DF_BASE__INST6_SEG1 0 +#define DF_BASE__INST6_SEG2 0 +#define DF_BASE__INST6_SEG3 0 +#define DF_BASE__INST6_SEG4 0 + +#define DIO_BASE__INST0_SEG0 0x02404000 +#define DIO_BASE__INST0_SEG1 0 +#define DIO_BASE__INST0_SEG2 0 +#define DIO_BASE__INST0_SEG3 0 +#define DIO_BASE__INST0_SEG4 0 + +#define DIO_BASE__INST1_SEG0 0 +#define DIO_BASE__INST1_SEG1 0 +#define DIO_BASE__INST1_SEG2 0 +#define DIO_BASE__INST1_SEG3 0 +#define DIO_BASE__INST1_SEG4 0 + +#define DIO_BASE__INST2_SEG0 0 +#define DIO_BASE__INST2_SEG1 0 +#define DIO_BASE__INST2_SEG2 0 +#define DIO_BASE__INST2_SEG3 0 +#define DIO_BASE__INST2_SEG4 0 + +#define DIO_BASE__INST3_SEG0 0 +#define DIO_BASE__INST3_SEG1 0 +#define DIO_BASE__INST3_SEG2 0 +#define DIO_BASE__INST3_SEG3 0 +#define DIO_BASE__INST3_SEG4 0 + +#define DIO_BASE__INST4_SEG0 0 +#define DIO_BASE__INST4_SEG1 0 +#define DIO_BASE__INST4_SEG2 0 +#define DIO_BASE__INST4_SEG3 0 +#define DIO_BASE__INST4_SEG4 0 + +#define DIO_BASE__INST5_SEG0 0 +#define DIO_BASE__INST5_SEG1 0 +#define DIO_BASE__INST5_SEG2 0 +#define DIO_BASE__INST5_SEG3 0 +#define DIO_BASE__INST5_SEG4 0 + +#define DIO_BASE__INST6_SEG0 0 +#define DIO_BASE__INST6_SEG1 0 +#define DIO_BASE__INST6_SEG2 0 +#define DIO_BASE__INST6_SEG3 0 +#define DIO_BASE__INST6_SEG4 0 + +#define DMU_BASE__INST0_SEG0 0x00000012 +#define DMU_BASE__INST0_SEG1 0x000000C0 +#define DMU_BASE__INST0_SEG2 0x000034C0 +#define DMU_BASE__INST0_SEG3 0x00009000 +#define DMU_BASE__INST0_SEG4 0x02403C00 + +#define DMU_BASE__INST1_SEG0 0 +#define DMU_BASE__INST1_SEG1 0 +#define DMU_BASE__INST1_SEG2 0 +#define DMU_BASE__INST1_SEG3 0 +#define DMU_BASE__INST1_SEG4 0 + +#define DMU_BASE__INST2_SEG0 0 +#define DMU_BASE__INST2_SEG1 0 +#define DMU_BASE__INST2_SEG2 0 +#define DMU_BASE__INST2_SEG3 0 +#define DMU_BASE__INST2_SEG4 0 + +#define DMU_BASE__INST3_SEG0 0 +#define DMU_BASE__INST3_SEG1 0 +#define DMU_BASE__INST3_SEG2 0 +#define DMU_BASE__INST3_SEG3 0 +#define DMU_BASE__INST3_SEG4 0 + +#define DMU_BASE__INST4_SEG0 0 +#define DMU_BASE__INST4_SEG1 0 +#define DMU_BASE__INST4_SEG2 0 +#define DMU_BASE__INST4_SEG3 0 +#define DMU_BASE__INST4_SEG4 0 + +#define DMU_BASE__INST5_SEG0 0 +#define DMU_BASE__INST5_SEG1 0 +#define DMU_BASE__INST5_SEG2 0 +#define DMU_BASE__INST5_SEG3 0 +#define DMU_BASE__INST5_SEG4 0 + +#define DMU_BASE__INST6_SEG0 0 +#define DMU_BASE__INST6_SEG1 0 +#define DMU_BASE__INST6_SEG2 0 +#define DMU_BASE__INST6_SEG3 0 +#define DMU_BASE__INST6_SEG4 0 + +#define DPCS_BASE__INST0_SEG0 0x00000012 +#define DPCS_BASE__INST0_SEG1 0x000000C0 +#define DPCS_BASE__INST0_SEG2 0x000034C0 +#define DPCS_BASE__INST0_SEG3 0x00009000 +#define DPCS_BASE__INST0_SEG4 0x02403C00 + +#define DPCS_BASE__INST1_SEG0 0 +#define DPCS_BASE__INST1_SEG1 0 +#define DPCS_BASE__INST1_SEG2 0 +#define DPCS_BASE__INST1_SEG3 0 +#define DPCS_BASE__INST1_SEG4 0 + +#define DPCS_BASE__INST2_SEG0 0 +#define DPCS_BASE__INST2_SEG1 0 +#define DPCS_BASE__INST2_SEG2 0 +#define DPCS_BASE__INST2_SEG3 0 +#define DPCS_BASE__INST2_SEG4 0 + +#define DPCS_BASE__INST3_SEG0 0 +#define DPCS_BASE__INST3_SEG1 0 +#define DPCS_BASE__INST3_SEG2 0 +#define DPCS_BASE__INST3_SEG3 0 +#define DPCS_BASE__INST3_SEG4 0 + +#define DPCS_BASE__INST4_SEG0 0 +#define DPCS_BASE__INST4_SEG1 0 +#define DPCS_BASE__INST4_SEG2 0 +#define DPCS_BASE__INST4_SEG3 0 +#define DPCS_BASE__INST4_SEG4 0 + +#define DPCS_BASE__INST5_SEG0 0 +#define DPCS_BASE__INST5_SEG1 0 +#define DPCS_BASE__INST5_SEG2 0 +#define DPCS_BASE__INST5_SEG3 0 +#define DPCS_BASE__INST5_SEG4 0 + +#define DPCS_BASE__INST6_SEG0 0 +#define DPCS_BASE__INST6_SEG1 0 +#define DPCS_BASE__INST6_SEG2 0 +#define DPCS_BASE__INST6_SEG3 0 +#define DPCS_BASE__INST6_SEG4 0 + +#define FUSE_BASE__INST0_SEG0 0x00017400 +#define FUSE_BASE__INST0_SEG1 0x02401400 +#define FUSE_BASE__INST0_SEG2 0 +#define FUSE_BASE__INST0_SEG3 0 +#define FUSE_BASE__INST0_SEG4 0 + +#define FUSE_BASE__INST1_SEG0 0 +#define FUSE_BASE__INST1_SEG1 0 +#define FUSE_BASE__INST1_SEG2 0 +#define FUSE_BASE__INST1_SEG3 0 +#define FUSE_BASE__INST1_SEG4 0 + +#define FUSE_BASE__INST2_SEG0 0 +#define FUSE_BASE__INST2_SEG1 0 +#define FUSE_BASE__INST2_SEG2 0 +#define FUSE_BASE__INST2_SEG3 0 +#define FUSE_BASE__INST2_SEG4 0 + +#define FUSE_BASE__INST3_SEG0 0 +#define FUSE_BASE__INST3_SEG1 0 +#define FUSE_BASE__INST3_SEG2 0 +#define FUSE_BASE__INST3_SEG3 0 +#define FUSE_BASE__INST3_SEG4 0 + +#define FUSE_BASE__INST4_SEG0 0 +#define FUSE_BASE__INST4_SEG1 0 +#define FUSE_BASE__INST4_SEG2 0 +#define FUSE_BASE__INST4_SEG3 0 +#define FUSE_BASE__INST4_SEG4 0 + +#define FUSE_BASE__INST5_SEG0 0 +#define FUSE_BASE__INST5_SEG1 0 +#define FUSE_BASE__INST5_SEG2 0 +#define FUSE_BASE__INST5_SEG3 0 +#define FUSE_BASE__INST5_SEG4 0 + +#define FUSE_BASE__INST6_SEG0 0 +#define FUSE_BASE__INST6_SEG1 0 +#define FUSE_BASE__INST6_SEG2 0 +#define FUSE_BASE__INST6_SEG3 0 +#define FUSE_BASE__INST6_SEG4 0 + +#define GC_BASE__INST0_SEG0 0x00001260 +#define GC_BASE__INST0_SEG1 0x0000A000 +#define GC_BASE__INST0_SEG2 0x02402C00 +#define GC_BASE__INST0_SEG3 0 +#define GC_BASE__INST0_SEG4 0 + +#define GC_BASE__INST1_SEG0 0 +#define GC_BASE__INST1_SEG1 0 +#define GC_BASE__INST1_SEG2 0 +#define GC_BASE__INST1_SEG3 0 +#define GC_BASE__INST1_SEG4 0 + +#define GC_BASE__INST2_SEG0 0 +#define GC_BASE__INST2_SEG1 0 +#define GC_BASE__INST2_SEG2 0 +#define GC_BASE__INST2_SEG3 0 +#define GC_BASE__INST2_SEG4 0 + +#define GC_BASE__INST3_SEG0 0 +#define GC_BASE__INST3_SEG1 0 +#define GC_BASE__INST3_SEG2 0 +#define GC_BASE__INST3_SEG3 0 +#define GC_BASE__INST3_SEG4 0 + +#define GC_BASE__INST4_SEG0 0 +#define GC_BASE__INST4_SEG1 0 +#define GC_BASE__INST4_SEG2 0 +#define GC_BASE__INST4_SEG3 0 +#define GC_BASE__INST4_SEG4 0 + +#define GC_BASE__INST5_SEG0 0 +#define GC_BASE__INST5_SEG1 0 +#define GC_BASE__INST5_SEG2 0 +#define GC_BASE__INST5_SEG3 0 +#define GC_BASE__INST5_SEG4 0 + +#define GC_BASE__INST6_SEG0 0 +#define GC_BASE__INST6_SEG1 0 +#define GC_BASE__INST6_SEG2 0 +#define GC_BASE__INST6_SEG3 0 +#define GC_BASE__INST6_SEG4 0 + +#define HDA_BASE__INST0_SEG0 0x004C0000 +#define HDA_BASE__INST0_SEG1 0x02404800 +#define HDA_BASE__INST0_SEG2 0 +#define HDA_BASE__INST0_SEG3 0 +#define HDA_BASE__INST0_SEG4 0 + +#define HDA_BASE__INST1_SEG0 0 +#define HDA_BASE__INST1_SEG1 0 +#define HDA_BASE__INST1_SEG2 0 +#define HDA_BASE__INST1_SEG3 0 +#define HDA_BASE__INST1_SEG4 0 + +#define HDA_BASE__INST2_SEG0 0 +#define HDA_BASE__INST2_SEG1 0 +#define HDA_BASE__INST2_SEG2 0 +#define HDA_BASE__INST2_SEG3 0 +#define HDA_BASE__INST2_SEG4 0 + +#define HDA_BASE__INST3_SEG0 0 +#define HDA_BASE__INST3_SEG1 0 +#define HDA_BASE__INST3_SEG2 0 +#define HDA_BASE__INST3_SEG3 0 +#define HDA_BASE__INST3_SEG4 0 + +#define HDA_BASE__INST4_SEG0 0 +#define HDA_BASE__INST4_SEG1 0 +#define HDA_BASE__INST4_SEG2 0 +#define HDA_BASE__INST4_SEG3 0 +#define HDA_BASE__INST4_SEG4 0 + +#define HDA_BASE__INST5_SEG0 0 +#define HDA_BASE__INST5_SEG1 0 +#define HDA_BASE__INST5_SEG2 0 +#define HDA_BASE__INST5_SEG3 0 +#define HDA_BASE__INST5_SEG4 0 + +#define HDA_BASE__INST6_SEG0 0 +#define HDA_BASE__INST6_SEG1 0 +#define HDA_BASE__INST6_SEG2 0 +#define HDA_BASE__INST6_SEG3 0 +#define HDA_BASE__INST6_SEG4 0 + +#define HDP_BASE__INST0_SEG0 0x00000F20 +#define HDP_BASE__INST0_SEG1 0x0240A400 +#define HDP_BASE__INST0_SEG2 0 +#define HDP_BASE__INST0_SEG3 0 +#define HDP_BASE__INST0_SEG4 0 + +#define HDP_BASE__INST1_SEG0 0 +#define HDP_BASE__INST1_SEG1 0 +#define HDP_BASE__INST1_SEG2 0 +#define HDP_BASE__INST1_SEG3 0 +#define HDP_BASE__INST1_SEG4 0 + +#define HDP_BASE__INST2_SEG0 0 +#define HDP_BASE__INST2_SEG1 0 +#define HDP_BASE__INST2_SEG2 0 +#define HDP_BASE__INST2_SEG3 0 +#define HDP_BASE__INST2_SEG4 0 + +#define HDP_BASE__INST3_SEG0 0 +#define HDP_BASE__INST3_SEG1 0 +#define HDP_BASE__INST3_SEG2 0 +#define HDP_BASE__INST3_SEG3 0 +#define HDP_BASE__INST3_SEG4 0 + +#define HDP_BASE__INST4_SEG0 0 +#define HDP_BASE__INST4_SEG1 0 +#define HDP_BASE__INST4_SEG2 0 +#define HDP_BASE__INST4_SEG3 0 +#define HDP_BASE__INST4_SEG4 0 + +#define HDP_BASE__INST5_SEG0 0 +#define HDP_BASE__INST5_SEG1 0 +#define HDP_BASE__INST5_SEG2 0 +#define HDP_BASE__INST5_SEG3 0 +#define HDP_BASE__INST5_SEG4 0 + +#define HDP_BASE__INST6_SEG0 0 +#define HDP_BASE__INST6_SEG1 0 +#define HDP_BASE__INST6_SEG2 0 +#define HDP_BASE__INST6_SEG3 0 +#define HDP_BASE__INST6_SEG4 0 + +#define MMHUB_BASE__INST0_SEG0 0x0001A000 +#define MMHUB_BASE__INST0_SEG1 0x02408800 +#define MMHUB_BASE__INST0_SEG2 0 +#define MMHUB_BASE__INST0_SEG3 0 +#define MMHUB_BASE__INST0_SEG4 0 + +#define MMHUB_BASE__INST1_SEG0 0 +#define MMHUB_BASE__INST1_SEG1 0 +#define MMHUB_BASE__INST1_SEG2 0 +#define MMHUB_BASE__INST1_SEG3 0 +#define MMHUB_BASE__INST1_SEG4 0 + +#define MMHUB_BASE__INST2_SEG0 0 +#define MMHUB_BASE__INST2_SEG1 0 +#define MMHUB_BASE__INST2_SEG2 0 +#define MMHUB_BASE__INST2_SEG3 0 +#define MMHUB_BASE__INST2_SEG4 0 + +#define MMHUB_BASE__INST3_SEG0 0 +#define MMHUB_BASE__INST3_SEG1 0 +#define MMHUB_BASE__INST3_SEG2 0 +#define MMHUB_BASE__INST3_SEG3 0 +#define MMHUB_BASE__INST3_SEG4 0 + +#define MMHUB_BASE__INST4_SEG0 0 +#define MMHUB_BASE__INST4_SEG1 0 +#define MMHUB_BASE__INST4_SEG2 0 +#define MMHUB_BASE__INST4_SEG3 0 +#define MMHUB_BASE__INST4_SEG4 0 + +#define MMHUB_BASE__INST5_SEG0 0 +#define MMHUB_BASE__INST5_SEG1 0 +#define MMHUB_BASE__INST5_SEG2 0 +#define MMHUB_BASE__INST5_SEG3 0 +#define MMHUB_BASE__INST5_SEG4 0 + +#define MMHUB_BASE__INST6_SEG0 0 +#define MMHUB_BASE__INST6_SEG1 0 +#define MMHUB_BASE__INST6_SEG2 0 +#define MMHUB_BASE__INST6_SEG3 0 +#define MMHUB_BASE__INST6_SEG4 0 + +#define MP0_BASE__INST0_SEG0 0x00016000 +#define MP0_BASE__INST0_SEG1 0x00DC0000 +#define MP0_BASE__INST0_SEG2 0x00E00000 +#define MP0_BASE__INST0_SEG3 0x00E40000 +#define MP0_BASE__INST0_SEG4 0x0243FC00 + +#define MP0_BASE__INST1_SEG0 0 +#define MP0_BASE__INST1_SEG1 0 +#define MP0_BASE__INST1_SEG2 0 +#define MP0_BASE__INST1_SEG3 0 +#define MP0_BASE__INST1_SEG4 0 + +#define MP0_BASE__INST2_SEG0 0 +#define MP0_BASE__INST2_SEG1 0 +#define MP0_BASE__INST2_SEG2 0 +#define MP0_BASE__INST2_SEG3 0 +#define MP0_BASE__INST2_SEG4 0 + +#define MP0_BASE__INST3_SEG0 0 +#define MP0_BASE__INST3_SEG1 0 +#define MP0_BASE__INST3_SEG2 0 +#define MP0_BASE__INST3_SEG3 0 +#define MP0_BASE__INST3_SEG4 0 + +#define MP0_BASE__INST4_SEG0 0 +#define MP0_BASE__INST4_SEG1 0 +#define MP0_BASE__INST4_SEG2 0 +#define MP0_BASE__INST4_SEG3 0 +#define MP0_BASE__INST4_SEG4 0 + +#define MP0_BASE__INST5_SEG0 0 +#define MP0_BASE__INST5_SEG1 0 +#define MP0_BASE__INST5_SEG2 0 +#define MP0_BASE__INST5_SEG3 0 +#define MP0_BASE__INST5_SEG4 0 + +#define MP0_BASE__INST6_SEG0 0 +#define MP0_BASE__INST6_SEG1 0 +#define MP0_BASE__INST6_SEG2 0 +#define MP0_BASE__INST6_SEG3 0 +#define MP0_BASE__INST6_SEG4 0 + +#define MP1_BASE__INST0_SEG0 0x00016000 +#define MP1_BASE__INST0_SEG1 0x00DC0000 +#define MP1_BASE__INST0_SEG2 0x00E00000 +#define MP1_BASE__INST0_SEG3 0x00E40000 +#define MP1_BASE__INST0_SEG4 0x0243FC00 + +#define MP1_BASE__INST1_SEG0 0 +#define MP1_BASE__INST1_SEG1 0 +#define MP1_BASE__INST1_SEG2 0 +#define MP1_BASE__INST1_SEG3 0 +#define MP1_BASE__INST1_SEG4 0 + +#define MP1_BASE__INST2_SEG0 0 +#define MP1_BASE__INST2_SEG1 0 +#define MP1_BASE__INST2_SEG2 0 +#define MP1_BASE__INST2_SEG3 0 +#define MP1_BASE__INST2_SEG4 0 + +#define MP1_BASE__INST3_SEG0 0 +#define MP1_BASE__INST3_SEG1 0 +#define MP1_BASE__INST3_SEG2 0 +#define MP1_BASE__INST3_SEG3 0 +#define MP1_BASE__INST3_SEG4 0 + +#define MP1_BASE__INST4_SEG0 0 +#define MP1_BASE__INST4_SEG1 0 +#define MP1_BASE__INST4_SEG2 0 +#define MP1_BASE__INST4_SEG3 0 +#define MP1_BASE__INST4_SEG4 0 + +#define MP1_BASE__INST5_SEG0 0 +#define MP1_BASE__INST5_SEG1 0 +#define MP1_BASE__INST5_SEG2 0 +#define MP1_BASE__INST5_SEG3 0 +#define MP1_BASE__INST5_SEG4 0 + +#define MP1_BASE__INST6_SEG0 0 +#define MP1_BASE__INST6_SEG1 0 +#define MP1_BASE__INST6_SEG2 0 +#define MP1_BASE__INST6_SEG3 0 +#define MP1_BASE__INST6_SEG4 0 + +#define NBIF0_BASE__INST0_SEG0 0x00000000 +#define NBIF0_BASE__INST0_SEG1 0x00000014 +#define NBIF0_BASE__INST0_SEG2 0x00000D20 +#define NBIF0_BASE__INST0_SEG3 0x00010400 +#define NBIF0_BASE__INST0_SEG4 0x0241B000 + +#define NBIF0_BASE__INST1_SEG0 0 +#define NBIF0_BASE__INST1_SEG1 0 +#define NBIF0_BASE__INST1_SEG2 0 +#define NBIF0_BASE__INST1_SEG3 0 +#define NBIF0_BASE__INST1_SEG4 0 + +#define NBIF0_BASE__INST2_SEG0 0 +#define NBIF0_BASE__INST2_SEG1 0 +#define NBIF0_BASE__INST2_SEG2 0 +#define NBIF0_BASE__INST2_SEG3 0 +#define NBIF0_BASE__INST2_SEG4 0 + +#define NBIF0_BASE__INST3_SEG0 0 +#define NBIF0_BASE__INST3_SEG1 0 +#define NBIF0_BASE__INST3_SEG2 0 +#define NBIF0_BASE__INST3_SEG3 0 +#define NBIF0_BASE__INST3_SEG4 0 + +#define NBIF0_BASE__INST4_SEG0 0 +#define NBIF0_BASE__INST4_SEG1 0 +#define NBIF0_BASE__INST4_SEG2 0 +#define NBIF0_BASE__INST4_SEG3 0 +#define NBIF0_BASE__INST4_SEG4 0 + +#define NBIF0_BASE__INST5_SEG0 0 +#define NBIF0_BASE__INST5_SEG1 0 +#define NBIF0_BASE__INST5_SEG2 0 +#define NBIF0_BASE__INST5_SEG3 0 +#define NBIF0_BASE__INST5_SEG4 0 + +#define NBIF0_BASE__INST6_SEG0 0 +#define NBIF0_BASE__INST6_SEG1 0 +#define NBIF0_BASE__INST6_SEG2 0 +#define NBIF0_BASE__INST6_SEG3 0 +#define NBIF0_BASE__INST6_SEG4 0 + +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 +#define OSSSYS_BASE__INST0_SEG1 0x0240A000 +#define OSSSYS_BASE__INST0_SEG2 0 +#define OSSSYS_BASE__INST0_SEG3 0 +#define OSSSYS_BASE__INST0_SEG4 0 + +#define OSSSYS_BASE__INST1_SEG0 0 +#define OSSSYS_BASE__INST1_SEG1 0 +#define OSSSYS_BASE__INST1_SEG2 0 +#define OSSSYS_BASE__INST1_SEG3 0 +#define OSSSYS_BASE__INST1_SEG4 0 + +#define OSSSYS_BASE__INST2_SEG0 0 +#define OSSSYS_BASE__INST2_SEG1 0 +#define OSSSYS_BASE__INST2_SEG2 0 +#define OSSSYS_BASE__INST2_SEG3 0 +#define OSSSYS_BASE__INST2_SEG4 0 + +#define OSSSYS_BASE__INST3_SEG0 0 +#define OSSSYS_BASE__INST3_SEG1 0 +#define OSSSYS_BASE__INST3_SEG2 0 +#define OSSSYS_BASE__INST3_SEG3 0 +#define OSSSYS_BASE__INST3_SEG4 0 + +#define OSSSYS_BASE__INST4_SEG0 0 +#define OSSSYS_BASE__INST4_SEG1 0 +#define OSSSYS_BASE__INST4_SEG2 0 +#define OSSSYS_BASE__INST4_SEG3 0 +#define OSSSYS_BASE__INST4_SEG4 0 + +#define OSSSYS_BASE__INST5_SEG0 0 +#define OSSSYS_BASE__INST5_SEG1 0 +#define OSSSYS_BASE__INST5_SEG2 0 +#define OSSSYS_BASE__INST5_SEG3 0 +#define OSSSYS_BASE__INST5_SEG4 0 + +#define OSSSYS_BASE__INST6_SEG0 0 +#define OSSSYS_BASE__INST6_SEG1 0 +#define OSSSYS_BASE__INST6_SEG2 0 +#define OSSSYS_BASE__INST6_SEG3 0 +#define OSSSYS_BASE__INST6_SEG4 0 + +#define PCIE0_BASE__INST0_SEG0 0x00000000 +#define PCIE0_BASE__INST0_SEG1 0x00000014 +#define PCIE0_BASE__INST0_SEG2 0x00000D20 +#define PCIE0_BASE__INST0_SEG3 0x00010400 +#define PCIE0_BASE__INST0_SEG4 0x0241B000 + +#define PCIE0_BASE__INST1_SEG0 0 +#define PCIE0_BASE__INST1_SEG1 0 +#define PCIE0_BASE__INST1_SEG2 0 +#define PCIE0_BASE__INST1_SEG3 0 +#define PCIE0_BASE__INST1_SEG4 0 + +#define PCIE0_BASE__INST2_SEG0 0 +#define PCIE0_BASE__INST2_SEG1 0 +#define PCIE0_BASE__INST2_SEG2 0 +#define PCIE0_BASE__INST2_SEG3 0 +#define PCIE0_BASE__INST2_SEG4 0 + +#define PCIE0_BASE__INST3_SEG0 0 +#define PCIE0_BASE__INST3_SEG1 0 +#define PCIE0_BASE__INST3_SEG2 0 +#define PCIE0_BASE__INST3_SEG3 0 +#define PCIE0_BASE__INST3_SEG4 0 + +#define PCIE0_BASE__INST4_SEG0 0 +#define PCIE0_BASE__INST4_SEG1 0 +#define PCIE0_BASE__INST4_SEG2 0 +#define PCIE0_BASE__INST4_SEG3 0 +#define PCIE0_BASE__INST4_SEG4 0 + +#define PCIE0_BASE__INST5_SEG0 0 +#define PCIE0_BASE__INST5_SEG1 0 +#define PCIE0_BASE__INST5_SEG2 0 +#define PCIE0_BASE__INST5_SEG3 0 +#define PCIE0_BASE__INST5_SEG4 0 + +#define PCIE0_BASE__INST6_SEG0 0 +#define PCIE0_BASE__INST6_SEG1 0 +#define PCIE0_BASE__INST6_SEG2 0 +#define PCIE0_BASE__INST6_SEG3 0 +#define PCIE0_BASE__INST6_SEG4 0 + +#define SDMA_BASE__INST0_SEG0 0x00001260 +#define SDMA_BASE__INST0_SEG1 0x0000A000 +#define SDMA_BASE__INST0_SEG2 0x02402C00 +#define SDMA_BASE__INST0_SEG3 0 +#define SDMA_BASE__INST0_SEG4 0 + +#define SDMA_BASE__INST1_SEG0 0x00001260 +#define SDMA_BASE__INST1_SEG1 0x0000A000 +#define SDMA_BASE__INST1_SEG2 0x02402C00 +#define SDMA_BASE__INST1_SEG3 0 +#define SDMA_BASE__INST1_SEG4 0 + +#define SDMA_BASE__INST2_SEG0 0 +#define SDMA_BASE__INST2_SEG1 0 +#define SDMA_BASE__INST2_SEG2 0 +#define SDMA_BASE__INST2_SEG3 0 +#define SDMA_BASE__INST2_SEG4 0 + +#define SDMA_BASE__INST3_SEG0 0 +#define SDMA_BASE__INST3_SEG1 0 +#define SDMA_BASE__INST3_SEG2 0 +#define SDMA_BASE__INST3_SEG3 0 +#define SDMA_BASE__INST3_SEG4 0 + +#define SDMA_BASE__INST4_SEG0 0 +#define SDMA_BASE__INST4_SEG1 0 +#define SDMA_BASE__INST4_SEG2 0 +#define SDMA_BASE__INST4_SEG3 0 +#define SDMA_BASE__INST4_SEG4 0 + +#define SDMA_BASE__INST5_SEG0 0 +#define SDMA_BASE__INST5_SEG1 0 +#define SDMA_BASE__INST5_SEG2 0 +#define SDMA_BASE__INST5_SEG3 0 +#define SDMA_BASE__INST5_SEG4 0 + +#define SDMA_BASE__INST6_SEG0 0 +#define SDMA_BASE__INST6_SEG1 0 +#define SDMA_BASE__INST6_SEG2 0 +#define SDMA_BASE__INST6_SEG3 0 +#define SDMA_BASE__INST6_SEG4 0 + +#define SMUIO_BASE__INST0_SEG0 0x00016800 +#define SMUIO_BASE__INST0_SEG1 0x00016A00 +#define SMUIO_BASE__INST0_SEG2 0x00440000 +#define SMUIO_BASE__INST0_SEG3 0x02401000 +#define SMUIO_BASE__INST0_SEG4 0 + +#define SMUIO_BASE__INST1_SEG0 0 +#define SMUIO_BASE__INST1_SEG1 0 +#define SMUIO_BASE__INST1_SEG2 0 +#define SMUIO_BASE__INST1_SEG3 0 +#define SMUIO_BASE__INST1_SEG4 0 + +#define SMUIO_BASE__INST2_SEG0 0 +#define SMUIO_BASE__INST2_SEG1 0 +#define SMUIO_BASE__INST2_SEG2 0 +#define SMUIO_BASE__INST2_SEG3 0 +#define SMUIO_BASE__INST2_SEG4 0 + +#define SMUIO_BASE__INST3_SEG0 0 +#define SMUIO_BASE__INST3_SEG1 0 +#define SMUIO_BASE__INST3_SEG2 0 +#define SMUIO_BASE__INST3_SEG3 0 +#define SMUIO_BASE__INST3_SEG4 0 + +#define SMUIO_BASE__INST4_SEG0 0 +#define SMUIO_BASE__INST4_SEG1 0 +#define SMUIO_BASE__INST4_SEG2 0 +#define SMUIO_BASE__INST4_SEG3 0 +#define SMUIO_BASE__INST4_SEG4 0 + +#define SMUIO_BASE__INST5_SEG0 0 +#define SMUIO_BASE__INST5_SEG1 0 +#define SMUIO_BASE__INST5_SEG2 0 +#define SMUIO_BASE__INST5_SEG3 0 +#define SMUIO_BASE__INST5_SEG4 0 + +#define SMUIO_BASE__INST6_SEG0 0 +#define SMUIO_BASE__INST6_SEG1 0 +#define SMUIO_BASE__INST6_SEG2 0 +#define SMUIO_BASE__INST6_SEG3 0 +#define SMUIO_BASE__INST6_SEG4 0 + +#define THM_BASE__INST0_SEG0 0x00016600 +#define THM_BASE__INST0_SEG1 0x02400C00 +#define THM_BASE__INST0_SEG2 0 +#define THM_BASE__INST0_SEG3 0 +#define THM_BASE__INST0_SEG4 0 + +#define THM_BASE__INST1_SEG0 0 +#define THM_BASE__INST1_SEG1 0 +#define THM_BASE__INST1_SEG2 0 +#define THM_BASE__INST1_SEG3 0 +#define THM_BASE__INST1_SEG4 0 + +#define THM_BASE__INST2_SEG0 0 +#define THM_BASE__INST2_SEG1 0 +#define THM_BASE__INST2_SEG2 0 +#define THM_BASE__INST2_SEG3 0 +#define THM_BASE__INST2_SEG4 0 + +#define THM_BASE__INST3_SEG0 0 +#define THM_BASE__INST3_SEG1 0 +#define THM_BASE__INST3_SEG2 0 +#define THM_BASE__INST3_SEG3 0 +#define THM_BASE__INST3_SEG4 0 + +#define THM_BASE__INST4_SEG0 0 +#define THM_BASE__INST4_SEG1 0 +#define THM_BASE__INST4_SEG2 0 +#define THM_BASE__INST4_SEG3 0 +#define THM_BASE__INST4_SEG4 0 + +#define THM_BASE__INST5_SEG0 0 +#define THM_BASE__INST5_SEG1 0 +#define THM_BASE__INST5_SEG2 0 +#define THM_BASE__INST5_SEG3 0 +#define THM_BASE__INST5_SEG4 0 + +#define THM_BASE__INST6_SEG0 0 +#define THM_BASE__INST6_SEG1 0 +#define THM_BASE__INST6_SEG2 0 +#define THM_BASE__INST6_SEG3 0 +#define THM_BASE__INST6_SEG4 0 + +#define UMC_BASE__INST0_SEG0 0x00014000 +#define UMC_BASE__INST0_SEG1 0x02425800 +#define UMC_BASE__INST0_SEG2 0 +#define UMC_BASE__INST0_SEG3 0 +#define UMC_BASE__INST0_SEG4 0 + +#define UMC_BASE__INST1_SEG0 0x00054000 +#define UMC_BASE__INST1_SEG1 0x02425C00 +#define UMC_BASE__INST1_SEG2 0 +#define UMC_BASE__INST1_SEG3 0 +#define UMC_BASE__INST1_SEG4 0 + +#define UMC_BASE__INST2_SEG0 0x00094000 +#define UMC_BASE__INST2_SEG1 0x02426000 +#define UMC_BASE__INST2_SEG2 0 +#define UMC_BASE__INST2_SEG3 0 +#define UMC_BASE__INST2_SEG4 0 + +#define UMC_BASE__INST3_SEG0 0x000D4000 +#define UMC_BASE__INST3_SEG1 0x02426400 +#define UMC_BASE__INST3_SEG2 0 +#define UMC_BASE__INST3_SEG3 0 +#define UMC_BASE__INST3_SEG4 0 + +#define UMC_BASE__INST4_SEG0 0 +#define UMC_BASE__INST4_SEG1 0 +#define UMC_BASE__INST4_SEG2 0 +#define UMC_BASE__INST4_SEG3 0 +#define UMC_BASE__INST4_SEG4 0 + +#define UMC_BASE__INST5_SEG0 0 +#define UMC_BASE__INST5_SEG1 0 +#define UMC_BASE__INST5_SEG2 0 +#define UMC_BASE__INST5_SEG3 0 +#define UMC_BASE__INST5_SEG4 0 + +#define UMC_BASE__INST6_SEG0 0 +#define UMC_BASE__INST6_SEG1 0 +#define UMC_BASE__INST6_SEG2 0 +#define UMC_BASE__INST6_SEG3 0 +#define UMC_BASE__INST6_SEG4 0 + +#define USB0_BASE__INST0_SEG0 0x0242A800 +#define USB0_BASE__INST0_SEG1 0x05B00000 +#define USB0_BASE__INST0_SEG2 0 +#define USB0_BASE__INST0_SEG3 0 +#define USB0_BASE__INST0_SEG4 0 + +#define USB0_BASE__INST1_SEG0 0 +#define USB0_BASE__INST1_SEG1 0 +#define USB0_BASE__INST1_SEG2 0 +#define USB0_BASE__INST1_SEG3 0 +#define USB0_BASE__INST1_SEG4 0 + +#define USB0_BASE__INST2_SEG0 0 +#define USB0_BASE__INST2_SEG1 0 +#define USB0_BASE__INST2_SEG2 0 +#define USB0_BASE__INST2_SEG3 0 +#define USB0_BASE__INST2_SEG4 0 + +#define USB0_BASE__INST3_SEG0 0 +#define USB0_BASE__INST3_SEG1 0 +#define USB0_BASE__INST3_SEG2 0 +#define USB0_BASE__INST3_SEG3 0 +#define USB0_BASE__INST3_SEG4 0 + +#define USB0_BASE__INST4_SEG0 0 +#define USB0_BASE__INST4_SEG1 0 +#define USB0_BASE__INST4_SEG2 0 +#define USB0_BASE__INST4_SEG3 0 +#define USB0_BASE__INST4_SEG4 0 + +#define USB0_BASE__INST5_SEG0 0 +#define USB0_BASE__INST5_SEG1 0 +#define USB0_BASE__INST5_SEG2 0 +#define USB0_BASE__INST5_SEG3 0 +#define USB0_BASE__INST5_SEG4 0 + +#define USB0_BASE__INST6_SEG0 0 +#define USB0_BASE__INST6_SEG1 0 +#define USB0_BASE__INST6_SEG2 0 +#define USB0_BASE__INST6_SEG3 0 +#define USB0_BASE__INST6_SEG4 0 + +#define UVD0_BASE__INST0_SEG0 0x00007800 +#define UVD0_BASE__INST0_SEG1 0x00007E00 +#define UVD0_BASE__INST0_SEG2 0x02403000 +#define UVD0_BASE__INST0_SEG3 0 +#define UVD0_BASE__INST0_SEG4 0 + +#define UVD0_BASE__INST1_SEG0 0 +#define UVD0_BASE__INST1_SEG1 0 +#define UVD0_BASE__INST1_SEG2 0 +#define UVD0_BASE__INST1_SEG3 0 +#define UVD0_BASE__INST1_SEG4 0 + +#define UVD0_BASE__INST2_SEG0 0 +#define UVD0_BASE__INST2_SEG1 0 +#define UVD0_BASE__INST2_SEG2 0 +#define UVD0_BASE__INST2_SEG3 0 +#define UVD0_BASE__INST2_SEG4 0 + +#define UVD0_BASE__INST3_SEG0 0 +#define UVD0_BASE__INST3_SEG1 0 +#define UVD0_BASE__INST3_SEG2 0 +#define UVD0_BASE__INST3_SEG3 0 +#define UVD0_BASE__INST3_SEG4 0 + +#define UVD0_BASE__INST4_SEG0 0 +#define UVD0_BASE__INST4_SEG1 0 +#define UVD0_BASE__INST4_SEG2 0 +#define UVD0_BASE__INST4_SEG3 0 +#define UVD0_BASE__INST4_SEG4 0 + +#define UVD0_BASE__INST5_SEG0 0 +#define UVD0_BASE__INST5_SEG1 0 +#define UVD0_BASE__INST5_SEG2 0 +#define UVD0_BASE__INST5_SEG3 0 +#define UVD0_BASE__INST5_SEG4 0 + +#define UVD0_BASE__INST6_SEG0 0 +#define UVD0_BASE__INST6_SEG1 0 +#define UVD0_BASE__INST6_SEG2 0 +#define UVD0_BASE__INST6_SEG3 0 +#define UVD0_BASE__INST6_SEG4 0 + +#endif diff --git a/src/amd/amdgpu/include/smu_v11_0.h b/src/amd/amdgpu/include/smu_v11_0.h new file mode 100644 index 0000000..f576578 --- /dev/null +++ b/src/amd/amdgpu/include/smu_v11_0.h @@ -0,0 +1,57 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __SMU_V11_0_H__ +#define __SMU_V11_0_H__ + +#define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF +#define SMU11_DRIVER_IF_VERSION_ARCT 0x17 +#define SMU11_DRIVER_IF_VERSION_NV10 0x36 +#define SMU11_DRIVER_IF_VERSION_NV12 0x33 +#define SMU11_DRIVER_IF_VERSION_NV14 0x36 +#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x34 +#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x3 + +/* MP Apertures */ +#define MP0_Public 0x03800000 +#define MP0_SRAM 0x03900000 +#define MP1_Public 0x03b00000 +#define MP1_SRAM 0x03c00004 + +/* address block */ +#define smnMP1_FIRMWARE_FLAGS 0x3010024 +#define smnMP0_FW_INTF 0x30101c0 +#define smnMP1_PUB_CTRL 0x3010b14 + +#define TEMP_RANGE_MIN (0) +#define TEMP_RANGE_MAX (80 * 1000) + +#define SMU11_TOOL_SIZE 0x19000 + +#define MAX_DPM_LEVELS 16 +#define MAX_PCIE_CONF 2 + +#define CTF_OFFSET_EDGE 5 +#define CTF_OFFSET_HOTSPOT 5 +#define CTF_OFFSET_MEM 5 + +#endif diff --git a/src/amd/amdgpu/include/vega10_ip_offset.h b/src/amd/amdgpu/include/vega10_ip_offset.h index 976dd2d..f9fe366 100644 --- a/src/amd/amdgpu/include/vega10_ip_offset.h +++ b/src/amd/amdgpu/include/vega10_ip_offset.h @@ -21,1245 +21,1242 @@ #ifndef _vega10_ip_offset_HEADER #define _vega10_ip_offset_HEADER -#define MAX_INSTANCE 5 -#define MAX_SEGMENT 5 +#define MAX_INSTANCE 5 +#define MAX_SEGMENT 5 struct IP_BASE_INSTANCE { - unsigned int segment[MAX_SEGMENT]; + unsigned int segment[MAX_SEGMENT]; }; struct IP_BASE { - struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; }; - -static const struct IP_BASE NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment -static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment -static const struct IP_BASE DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; // not exist -static const struct IP_BASE DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; // not exist -static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; // not exist -static const struct IP_BASE DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; // not exist -static const struct IP_BASE DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers -static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; // not exist -static const struct IP_BASE SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; // not exist -static const struct IP_BASE L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } }, - { { 0x00016E00, 0, 0, 0, 0 } }, - { { 0x00017000, 0, 0, 0, 0 } }, - { { 0x00017200, 0, 0, 0, 0 } }, - { { 0x00017E00, 0, 0, 0, 0 } } } }; -static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; - - -#define NBIF_BASE__INST0_SEG0 0x00000000 -#define NBIF_BASE__INST0_SEG1 0x00000014 -#define NBIF_BASE__INST0_SEG2 0x00000D20 -#define NBIF_BASE__INST0_SEG3 0x00010400 -#define NBIF_BASE__INST0_SEG4 0 - -#define NBIF_BASE__INST1_SEG0 0 -#define NBIF_BASE__INST1_SEG1 0 -#define NBIF_BASE__INST1_SEG2 0 -#define NBIF_BASE__INST1_SEG3 0 -#define NBIF_BASE__INST1_SEG4 0 - -#define NBIF_BASE__INST2_SEG0 0 -#define NBIF_BASE__INST2_SEG1 0 -#define NBIF_BASE__INST2_SEG2 0 -#define NBIF_BASE__INST2_SEG3 0 -#define NBIF_BASE__INST2_SEG4 0 - -#define NBIF_BASE__INST3_SEG0 0 -#define NBIF_BASE__INST3_SEG1 0 -#define NBIF_BASE__INST3_SEG2 0 -#define NBIF_BASE__INST3_SEG3 0 -#define NBIF_BASE__INST3_SEG4 0 - -#define NBIF_BASE__INST4_SEG0 0 -#define NBIF_BASE__INST4_SEG1 0 -#define NBIF_BASE__INST4_SEG2 0 -#define NBIF_BASE__INST4_SEG3 0 -#define NBIF_BASE__INST4_SEG4 0 - -#define NBIO_BASE__INST0_SEG0 0x00000000 -#define NBIO_BASE__INST0_SEG1 0x00000014 -#define NBIO_BASE__INST0_SEG2 0x00000D20 -#define NBIO_BASE__INST0_SEG3 0x00010400 -#define NBIO_BASE__INST0_SEG4 0 - -#define NBIO_BASE__INST1_SEG0 0 -#define NBIO_BASE__INST1_SEG1 0 -#define NBIO_BASE__INST1_SEG2 0 -#define NBIO_BASE__INST1_SEG3 0 -#define NBIO_BASE__INST1_SEG4 0 - -#define NBIO_BASE__INST2_SEG0 0 -#define NBIO_BASE__INST2_SEG1 0 -#define NBIO_BASE__INST2_SEG2 0 -#define NBIO_BASE__INST2_SEG3 0 -#define NBIO_BASE__INST2_SEG4 0 - -#define NBIO_BASE__INST3_SEG0 0 -#define NBIO_BASE__INST3_SEG1 0 -#define NBIO_BASE__INST3_SEG2 0 -#define NBIO_BASE__INST3_SEG3 0 -#define NBIO_BASE__INST3_SEG4 0 - -#define NBIO_BASE__INST4_SEG0 0 -#define NBIO_BASE__INST4_SEG1 0 -#define NBIO_BASE__INST4_SEG2 0 -#define NBIO_BASE__INST4_SEG3 0 -#define NBIO_BASE__INST4_SEG4 0 - -#define DCE_BASE__INST0_SEG0 0x00000012 -#define DCE_BASE__INST0_SEG1 0x000000C0 -#define DCE_BASE__INST0_SEG2 0x000034C0 -#define DCE_BASE__INST0_SEG3 0 -#define DCE_BASE__INST0_SEG4 0 - -#define DCE_BASE__INST1_SEG0 0 -#define DCE_BASE__INST1_SEG1 0 -#define DCE_BASE__INST1_SEG2 0 -#define DCE_BASE__INST1_SEG3 0 -#define DCE_BASE__INST1_SEG4 0 - -#define DCE_BASE__INST2_SEG0 0 -#define DCE_BASE__INST2_SEG1 0 -#define DCE_BASE__INST2_SEG2 0 -#define DCE_BASE__INST2_SEG3 0 -#define DCE_BASE__INST2_SEG4 0 - -#define DCE_BASE__INST3_SEG0 0 -#define DCE_BASE__INST3_SEG1 0 -#define DCE_BASE__INST3_SEG2 0 -#define DCE_BASE__INST3_SEG3 0 -#define DCE_BASE__INST3_SEG4 0 - -#define DCE_BASE__INST4_SEG0 0 -#define DCE_BASE__INST4_SEG1 0 -#define DCE_BASE__INST4_SEG2 0 -#define DCE_BASE__INST4_SEG3 0 -#define DCE_BASE__INST4_SEG4 0 - -#define DCN_BASE__INST0_SEG0 0x00000012 -#define DCN_BASE__INST0_SEG1 0x000000C0 -#define DCN_BASE__INST0_SEG2 0x000034C0 -#define DCN_BASE__INST0_SEG3 0 -#define DCN_BASE__INST0_SEG4 0 - -#define DCN_BASE__INST1_SEG0 0 -#define DCN_BASE__INST1_SEG1 0 -#define DCN_BASE__INST1_SEG2 0 -#define DCN_BASE__INST1_SEG3 0 -#define DCN_BASE__INST1_SEG4 0 - -#define DCN_BASE__INST2_SEG0 0 -#define DCN_BASE__INST2_SEG1 0 -#define DCN_BASE__INST2_SEG2 0 -#define DCN_BASE__INST2_SEG3 0 -#define DCN_BASE__INST2_SEG4 0 - -#define DCN_BASE__INST3_SEG0 0 -#define DCN_BASE__INST3_SEG1 0 -#define DCN_BASE__INST3_SEG2 0 -#define DCN_BASE__INST3_SEG3 0 -#define DCN_BASE__INST3_SEG4 0 - -#define DCN_BASE__INST4_SEG0 0 -#define DCN_BASE__INST4_SEG1 0 -#define DCN_BASE__INST4_SEG2 0 -#define DCN_BASE__INST4_SEG3 0 -#define DCN_BASE__INST4_SEG4 0 - -#define MP0_BASE__INST0_SEG0 0x00016000 -#define MP0_BASE__INST0_SEG1 0 -#define MP0_BASE__INST0_SEG2 0 -#define MP0_BASE__INST0_SEG3 0 -#define MP0_BASE__INST0_SEG4 0 - -#define MP0_BASE__INST1_SEG0 0 -#define MP0_BASE__INST1_SEG1 0 -#define MP0_BASE__INST1_SEG2 0 -#define MP0_BASE__INST1_SEG3 0 -#define MP0_BASE__INST1_SEG4 0 - -#define MP0_BASE__INST2_SEG0 0 -#define MP0_BASE__INST2_SEG1 0 -#define MP0_BASE__INST2_SEG2 0 -#define MP0_BASE__INST2_SEG3 0 -#define MP0_BASE__INST2_SEG4 0 - -#define MP0_BASE__INST3_SEG0 0 -#define MP0_BASE__INST3_SEG1 0 -#define MP0_BASE__INST3_SEG2 0 -#define MP0_BASE__INST3_SEG3 0 -#define MP0_BASE__INST3_SEG4 0 - -#define MP0_BASE__INST4_SEG0 0 -#define MP0_BASE__INST4_SEG1 0 -#define MP0_BASE__INST4_SEG2 0 -#define MP0_BASE__INST4_SEG3 0 -#define MP0_BASE__INST4_SEG4 0 - -#define MP1_BASE__INST0_SEG0 0x00016200 -#define MP1_BASE__INST0_SEG1 0 -#define MP1_BASE__INST0_SEG2 0 -#define MP1_BASE__INST0_SEG3 0 -#define MP1_BASE__INST0_SEG4 0 - -#define MP1_BASE__INST1_SEG0 0 -#define MP1_BASE__INST1_SEG1 0 -#define MP1_BASE__INST1_SEG2 0 -#define MP1_BASE__INST1_SEG3 0 -#define MP1_BASE__INST1_SEG4 0 - -#define MP1_BASE__INST2_SEG0 0 -#define MP1_BASE__INST2_SEG1 0 -#define MP1_BASE__INST2_SEG2 0 -#define MP1_BASE__INST2_SEG3 0 -#define MP1_BASE__INST2_SEG4 0 - -#define MP1_BASE__INST3_SEG0 0 -#define MP1_BASE__INST3_SEG1 0 -#define MP1_BASE__INST3_SEG2 0 -#define MP1_BASE__INST3_SEG3 0 -#define MP1_BASE__INST3_SEG4 0 - -#define MP1_BASE__INST4_SEG0 0 -#define MP1_BASE__INST4_SEG1 0 -#define MP1_BASE__INST4_SEG2 0 -#define MP1_BASE__INST4_SEG3 0 -#define MP1_BASE__INST4_SEG4 0 - -#define MP2_BASE__INST0_SEG0 0x00016400 -#define MP2_BASE__INST0_SEG1 0 -#define MP2_BASE__INST0_SEG2 0 -#define MP2_BASE__INST0_SEG3 0 -#define MP2_BASE__INST0_SEG4 0 - -#define MP2_BASE__INST1_SEG0 0 -#define MP2_BASE__INST1_SEG1 0 -#define MP2_BASE__INST1_SEG2 0 -#define MP2_BASE__INST1_SEG3 0 -#define MP2_BASE__INST1_SEG4 0 - -#define MP2_BASE__INST2_SEG0 0 -#define MP2_BASE__INST2_SEG1 0 -#define MP2_BASE__INST2_SEG2 0 -#define MP2_BASE__INST2_SEG3 0 -#define MP2_BASE__INST2_SEG4 0 - -#define MP2_BASE__INST3_SEG0 0 -#define MP2_BASE__INST3_SEG1 0 -#define MP2_BASE__INST3_SEG2 0 -#define MP2_BASE__INST3_SEG3 0 -#define MP2_BASE__INST3_SEG4 0 - -#define MP2_BASE__INST4_SEG0 0 -#define MP2_BASE__INST4_SEG1 0 -#define MP2_BASE__INST4_SEG2 0 -#define MP2_BASE__INST4_SEG3 0 -#define MP2_BASE__INST4_SEG4 0 - -#define DF_BASE__INST0_SEG0 0x00007000 -#define DF_BASE__INST0_SEG1 0 -#define DF_BASE__INST0_SEG2 0 -#define DF_BASE__INST0_SEG3 0 -#define DF_BASE__INST0_SEG4 0 - -#define DF_BASE__INST1_SEG0 0 -#define DF_BASE__INST1_SEG1 0 -#define DF_BASE__INST1_SEG2 0 -#define DF_BASE__INST1_SEG3 0 -#define DF_BASE__INST1_SEG4 0 - -#define DF_BASE__INST2_SEG0 0 -#define DF_BASE__INST2_SEG1 0 -#define DF_BASE__INST2_SEG2 0 -#define DF_BASE__INST2_SEG3 0 -#define DF_BASE__INST2_SEG4 0 - -#define DF_BASE__INST3_SEG0 0 -#define DF_BASE__INST3_SEG1 0 -#define DF_BASE__INST3_SEG2 0 -#define DF_BASE__INST3_SEG3 0 -#define DF_BASE__INST3_SEG4 0 - -#define DF_BASE__INST4_SEG0 0 -#define DF_BASE__INST4_SEG1 0 -#define DF_BASE__INST4_SEG2 0 -#define DF_BASE__INST4_SEG3 0 -#define DF_BASE__INST4_SEG4 0 - -#define UVD_BASE__INST0_SEG0 0x00007800 -#define UVD_BASE__INST0_SEG1 0x00007E00 -#define UVD_BASE__INST0_SEG2 0 -#define UVD_BASE__INST0_SEG3 0 -#define UVD_BASE__INST0_SEG4 0 - -#define UVD_BASE__INST1_SEG0 0 -#define UVD_BASE__INST1_SEG1 0 -#define UVD_BASE__INST1_SEG2 0 -#define UVD_BASE__INST1_SEG3 0 -#define UVD_BASE__INST1_SEG4 0 - -#define UVD_BASE__INST2_SEG0 0 -#define UVD_BASE__INST2_SEG1 0 -#define UVD_BASE__INST2_SEG2 0 -#define UVD_BASE__INST2_SEG3 0 -#define UVD_BASE__INST2_SEG4 0 - -#define UVD_BASE__INST3_SEG0 0 -#define UVD_BASE__INST3_SEG1 0 -#define UVD_BASE__INST3_SEG2 0 -#define UVD_BASE__INST3_SEG3 0 -#define UVD_BASE__INST3_SEG4 0 - -#define UVD_BASE__INST4_SEG0 0 -#define UVD_BASE__INST4_SEG1 0 -#define UVD_BASE__INST4_SEG2 0 -#define UVD_BASE__INST4_SEG3 0 -#define UVD_BASE__INST4_SEG4 0 - -#define VCN_BASE__INST0_SEG0 0x00007800 -#define VCN_BASE__INST0_SEG1 0x00007E00 -#define VCN_BASE__INST0_SEG2 0 -#define VCN_BASE__INST0_SEG3 0 -#define VCN_BASE__INST0_SEG4 0 - -#define VCN_BASE__INST1_SEG0 0 -#define VCN_BASE__INST1_SEG1 0 -#define VCN_BASE__INST1_SEG2 0 -#define VCN_BASE__INST1_SEG3 0 -#define VCN_BASE__INST1_SEG4 0 - -#define VCN_BASE__INST2_SEG0 0 -#define VCN_BASE__INST2_SEG1 0 -#define VCN_BASE__INST2_SEG2 0 -#define VCN_BASE__INST2_SEG3 0 -#define VCN_BASE__INST2_SEG4 0 - -#define VCN_BASE__INST3_SEG0 0 -#define VCN_BASE__INST3_SEG1 0 -#define VCN_BASE__INST3_SEG2 0 -#define VCN_BASE__INST3_SEG3 0 -#define VCN_BASE__INST3_SEG4 0 - -#define VCN_BASE__INST4_SEG0 0 -#define VCN_BASE__INST4_SEG1 0 -#define VCN_BASE__INST4_SEG2 0 -#define VCN_BASE__INST4_SEG3 0 -#define VCN_BASE__INST4_SEG4 0 - -#define DBGU_BASE__INST0_SEG0 0x00000180 -#define DBGU_BASE__INST0_SEG1 0x000001A0 -#define DBGU_BASE__INST0_SEG2 0 -#define DBGU_BASE__INST0_SEG3 0 -#define DBGU_BASE__INST0_SEG4 0 - -#define DBGU_BASE__INST1_SEG0 0 -#define DBGU_BASE__INST1_SEG1 0 -#define DBGU_BASE__INST1_SEG2 0 -#define DBGU_BASE__INST1_SEG3 0 -#define DBGU_BASE__INST1_SEG4 0 - -#define DBGU_BASE__INST2_SEG0 0 -#define DBGU_BASE__INST2_SEG1 0 -#define DBGU_BASE__INST2_SEG2 0 -#define DBGU_BASE__INST2_SEG3 0 -#define DBGU_BASE__INST2_SEG4 0 - -#define DBGU_BASE__INST3_SEG0 0 -#define DBGU_BASE__INST3_SEG1 0 -#define DBGU_BASE__INST3_SEG2 0 -#define DBGU_BASE__INST3_SEG3 0 -#define DBGU_BASE__INST3_SEG4 0 - -#define DBGU_BASE__INST4_SEG0 0 -#define DBGU_BASE__INST4_SEG1 0 -#define DBGU_BASE__INST4_SEG2 0 -#define DBGU_BASE__INST4_SEG3 0 -#define DBGU_BASE__INST4_SEG4 0 - -#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0 -#define DBGU_NBIO_BASE__INST0_SEG1 0 -#define DBGU_NBIO_BASE__INST0_SEG2 0 -#define DBGU_NBIO_BASE__INST0_SEG3 0 -#define DBGU_NBIO_BASE__INST0_SEG4 0 - -#define DBGU_NBIO_BASE__INST1_SEG0 0 -#define DBGU_NBIO_BASE__INST1_SEG1 0 -#define DBGU_NBIO_BASE__INST1_SEG2 0 -#define DBGU_NBIO_BASE__INST1_SEG3 0 -#define DBGU_NBIO_BASE__INST1_SEG4 0 - -#define DBGU_NBIO_BASE__INST2_SEG0 0 -#define DBGU_NBIO_BASE__INST2_SEG1 0 -#define DBGU_NBIO_BASE__INST2_SEG2 0 -#define DBGU_NBIO_BASE__INST2_SEG3 0 -#define DBGU_NBIO_BASE__INST2_SEG4 0 - -#define DBGU_NBIO_BASE__INST3_SEG0 0 -#define DBGU_NBIO_BASE__INST3_SEG1 0 -#define DBGU_NBIO_BASE__INST3_SEG2 0 -#define DBGU_NBIO_BASE__INST3_SEG3 0 -#define DBGU_NBIO_BASE__INST3_SEG4 0 - -#define DBGU_NBIO_BASE__INST4_SEG0 0 -#define DBGU_NBIO_BASE__INST4_SEG1 0 -#define DBGU_NBIO_BASE__INST4_SEG2 0 -#define DBGU_NBIO_BASE__INST4_SEG3 0 -#define DBGU_NBIO_BASE__INST4_SEG4 0 - -#define DBGU_IO_BASE__INST0_SEG0 0x000001E0 -#define DBGU_IO_BASE__INST0_SEG1 0 -#define DBGU_IO_BASE__INST0_SEG2 0 -#define DBGU_IO_BASE__INST0_SEG3 0 -#define DBGU_IO_BASE__INST0_SEG4 0 - -#define DBGU_IO_BASE__INST1_SEG0 0 -#define DBGU_IO_BASE__INST1_SEG1 0 -#define DBGU_IO_BASE__INST1_SEG2 0 -#define DBGU_IO_BASE__INST1_SEG3 0 -#define DBGU_IO_BASE__INST1_SEG4 0 - -#define DBGU_IO_BASE__INST2_SEG0 0 -#define DBGU_IO_BASE__INST2_SEG1 0 -#define DBGU_IO_BASE__INST2_SEG2 0 -#define DBGU_IO_BASE__INST2_SEG3 0 -#define DBGU_IO_BASE__INST2_SEG4 0 - -#define DBGU_IO_BASE__INST3_SEG0 0 -#define DBGU_IO_BASE__INST3_SEG1 0 -#define DBGU_IO_BASE__INST3_SEG2 0 -#define DBGU_IO_BASE__INST3_SEG3 0 -#define DBGU_IO_BASE__INST3_SEG4 0 - -#define DBGU_IO_BASE__INST4_SEG0 0 -#define DBGU_IO_BASE__INST4_SEG1 0 -#define DBGU_IO_BASE__INST4_SEG2 0 -#define DBGU_IO_BASE__INST4_SEG3 0 -#define DBGU_IO_BASE__INST4_SEG4 0 - -#define DFX_DAP_BASE__INST0_SEG0 0x000005A0 -#define DFX_DAP_BASE__INST0_SEG1 0 -#define DFX_DAP_BASE__INST0_SEG2 0 -#define DFX_DAP_BASE__INST0_SEG3 0 -#define DFX_DAP_BASE__INST0_SEG4 0 - -#define DFX_DAP_BASE__INST1_SEG0 0 -#define DFX_DAP_BASE__INST1_SEG1 0 -#define DFX_DAP_BASE__INST1_SEG2 0 -#define DFX_DAP_BASE__INST1_SEG3 0 -#define DFX_DAP_BASE__INST1_SEG4 0 - -#define DFX_DAP_BASE__INST2_SEG0 0 -#define DFX_DAP_BASE__INST2_SEG1 0 -#define DFX_DAP_BASE__INST2_SEG2 0 -#define DFX_DAP_BASE__INST2_SEG3 0 -#define DFX_DAP_BASE__INST2_SEG4 0 - -#define DFX_DAP_BASE__INST3_SEG0 0 -#define DFX_DAP_BASE__INST3_SEG1 0 -#define DFX_DAP_BASE__INST3_SEG2 0 -#define DFX_DAP_BASE__INST3_SEG3 0 -#define DFX_DAP_BASE__INST3_SEG4 0 - -#define DFX_DAP_BASE__INST4_SEG0 0 -#define DFX_DAP_BASE__INST4_SEG1 0 -#define DFX_DAP_BASE__INST4_SEG2 0 -#define DFX_DAP_BASE__INST4_SEG3 0 -#define DFX_DAP_BASE__INST4_SEG4 0 - -#define DFX_BASE__INST0_SEG0 0x00000580 -#define DFX_BASE__INST0_SEG1 0 -#define DFX_BASE__INST0_SEG2 0 -#define DFX_BASE__INST0_SEG3 0 -#define DFX_BASE__INST0_SEG4 0 - -#define DFX_BASE__INST1_SEG0 0 -#define DFX_BASE__INST1_SEG1 0 -#define DFX_BASE__INST1_SEG2 0 -#define DFX_BASE__INST1_SEG3 0 -#define DFX_BASE__INST1_SEG4 0 - -#define DFX_BASE__INST2_SEG0 0 -#define DFX_BASE__INST2_SEG1 0 -#define DFX_BASE__INST2_SEG2 0 -#define DFX_BASE__INST2_SEG3 0 -#define DFX_BASE__INST2_SEG4 0 - -#define DFX_BASE__INST3_SEG0 0 -#define DFX_BASE__INST3_SEG1 0 -#define DFX_BASE__INST3_SEG2 0 -#define DFX_BASE__INST3_SEG3 0 -#define DFX_BASE__INST3_SEG4 0 - -#define DFX_BASE__INST4_SEG0 0 -#define DFX_BASE__INST4_SEG1 0 -#define DFX_BASE__INST4_SEG2 0 -#define DFX_BASE__INST4_SEG3 0 -#define DFX_BASE__INST4_SEG4 0 - -#define ISP_BASE__INST0_SEG0 0x00018000 -#define ISP_BASE__INST0_SEG1 0 -#define ISP_BASE__INST0_SEG2 0 -#define ISP_BASE__INST0_SEG3 0 -#define ISP_BASE__INST0_SEG4 0 - -#define ISP_BASE__INST1_SEG0 0 -#define ISP_BASE__INST1_SEG1 0 -#define ISP_BASE__INST1_SEG2 0 -#define ISP_BASE__INST1_SEG3 0 -#define ISP_BASE__INST1_SEG4 0 - -#define ISP_BASE__INST2_SEG0 0 -#define ISP_BASE__INST2_SEG1 0 -#define ISP_BASE__INST2_SEG2 0 -#define ISP_BASE__INST2_SEG3 0 -#define ISP_BASE__INST2_SEG4 0 - -#define ISP_BASE__INST3_SEG0 0 -#define ISP_BASE__INST3_SEG1 0 -#define ISP_BASE__INST3_SEG2 0 -#define ISP_BASE__INST3_SEG3 0 -#define ISP_BASE__INST3_SEG4 0 - -#define ISP_BASE__INST4_SEG0 0 -#define ISP_BASE__INST4_SEG1 0 -#define ISP_BASE__INST4_SEG2 0 -#define ISP_BASE__INST4_SEG3 0 -#define ISP_BASE__INST4_SEG4 0 - -#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0 -#define SYSTEMHUB_BASE__INST0_SEG1 0 -#define SYSTEMHUB_BASE__INST0_SEG2 0 -#define SYSTEMHUB_BASE__INST0_SEG3 0 -#define SYSTEMHUB_BASE__INST0_SEG4 0 - -#define SYSTEMHUB_BASE__INST1_SEG0 0 -#define SYSTEMHUB_BASE__INST1_SEG1 0 -#define SYSTEMHUB_BASE__INST1_SEG2 0 -#define SYSTEMHUB_BASE__INST1_SEG3 0 -#define SYSTEMHUB_BASE__INST1_SEG4 0 - -#define SYSTEMHUB_BASE__INST2_SEG0 0 -#define SYSTEMHUB_BASE__INST2_SEG1 0 -#define SYSTEMHUB_BASE__INST2_SEG2 0 -#define SYSTEMHUB_BASE__INST2_SEG3 0 -#define SYSTEMHUB_BASE__INST2_SEG4 0 - -#define SYSTEMHUB_BASE__INST3_SEG0 0 -#define SYSTEMHUB_BASE__INST3_SEG1 0 -#define SYSTEMHUB_BASE__INST3_SEG2 0 -#define SYSTEMHUB_BASE__INST3_SEG3 0 -#define SYSTEMHUB_BASE__INST3_SEG4 0 - -#define SYSTEMHUB_BASE__INST4_SEG0 0 -#define SYSTEMHUB_BASE__INST4_SEG1 0 -#define SYSTEMHUB_BASE__INST4_SEG2 0 -#define SYSTEMHUB_BASE__INST4_SEG3 0 -#define SYSTEMHUB_BASE__INST4_SEG4 0 - -#define L2IMU_BASE__INST0_SEG0 0x00007DC0 -#define L2IMU_BASE__INST0_SEG1 0 -#define L2IMU_BASE__INST0_SEG2 0 -#define L2IMU_BASE__INST0_SEG3 0 -#define L2IMU_BASE__INST0_SEG4 0 - -#define L2IMU_BASE__INST1_SEG0 0 -#define L2IMU_BASE__INST1_SEG1 0 -#define L2IMU_BASE__INST1_SEG2 0 -#define L2IMU_BASE__INST1_SEG3 0 -#define L2IMU_BASE__INST1_SEG4 0 - -#define L2IMU_BASE__INST2_SEG0 0 -#define L2IMU_BASE__INST2_SEG1 0 -#define L2IMU_BASE__INST2_SEG2 0 -#define L2IMU_BASE__INST2_SEG3 0 -#define L2IMU_BASE__INST2_SEG4 0 - -#define L2IMU_BASE__INST3_SEG0 0 -#define L2IMU_BASE__INST3_SEG1 0 -#define L2IMU_BASE__INST3_SEG2 0 -#define L2IMU_BASE__INST3_SEG3 0 -#define L2IMU_BASE__INST3_SEG4 0 - -#define L2IMU_BASE__INST4_SEG0 0 -#define L2IMU_BASE__INST4_SEG1 0 -#define L2IMU_BASE__INST4_SEG2 0 -#define L2IMU_BASE__INST4_SEG3 0 -#define L2IMU_BASE__INST4_SEG4 0 - -#define IOHC_BASE__INST0_SEG0 0x00010000 -#define IOHC_BASE__INST0_SEG1 0 -#define IOHC_BASE__INST0_SEG2 0 -#define IOHC_BASE__INST0_SEG3 0 -#define IOHC_BASE__INST0_SEG4 0 - -#define IOHC_BASE__INST1_SEG0 0 -#define IOHC_BASE__INST1_SEG1 0 -#define IOHC_BASE__INST1_SEG2 0 -#define IOHC_BASE__INST1_SEG3 0 -#define IOHC_BASE__INST1_SEG4 0 - -#define IOHC_BASE__INST2_SEG0 0 -#define IOHC_BASE__INST2_SEG1 0 -#define IOHC_BASE__INST2_SEG2 0 -#define IOHC_BASE__INST2_SEG3 0 -#define IOHC_BASE__INST2_SEG4 0 - -#define IOHC_BASE__INST3_SEG0 0 -#define IOHC_BASE__INST3_SEG1 0 -#define IOHC_BASE__INST3_SEG2 0 -#define IOHC_BASE__INST3_SEG3 0 -#define IOHC_BASE__INST3_SEG4 0 - -#define IOHC_BASE__INST4_SEG0 0 -#define IOHC_BASE__INST4_SEG1 0 -#define IOHC_BASE__INST4_SEG2 0 -#define IOHC_BASE__INST4_SEG3 0 -#define IOHC_BASE__INST4_SEG4 0 - -#define ATHUB_BASE__INST0_SEG0 0x00000C20 -#define ATHUB_BASE__INST0_SEG1 0 -#define ATHUB_BASE__INST0_SEG2 0 -#define ATHUB_BASE__INST0_SEG3 0 -#define ATHUB_BASE__INST0_SEG4 0 - -#define ATHUB_BASE__INST1_SEG0 0 -#define ATHUB_BASE__INST1_SEG1 0 -#define ATHUB_BASE__INST1_SEG2 0 -#define ATHUB_BASE__INST1_SEG3 0 -#define ATHUB_BASE__INST1_SEG4 0 - -#define ATHUB_BASE__INST2_SEG0 0 -#define ATHUB_BASE__INST2_SEG1 0 -#define ATHUB_BASE__INST2_SEG2 0 -#define ATHUB_BASE__INST2_SEG3 0 -#define ATHUB_BASE__INST2_SEG4 0 - -#define ATHUB_BASE__INST3_SEG0 0 -#define ATHUB_BASE__INST3_SEG1 0 -#define ATHUB_BASE__INST3_SEG2 0 -#define ATHUB_BASE__INST3_SEG3 0 -#define ATHUB_BASE__INST3_SEG4 0 - -#define ATHUB_BASE__INST4_SEG0 0 -#define ATHUB_BASE__INST4_SEG1 0 -#define ATHUB_BASE__INST4_SEG2 0 -#define ATHUB_BASE__INST4_SEG3 0 -#define ATHUB_BASE__INST4_SEG4 0 - -#define VCE_BASE__INST0_SEG0 0x00007E00 -#define VCE_BASE__INST0_SEG1 0x00048800 -#define VCE_BASE__INST0_SEG2 0 -#define VCE_BASE__INST0_SEG3 0 -#define VCE_BASE__INST0_SEG4 0 - -#define VCE_BASE__INST1_SEG0 0 -#define VCE_BASE__INST1_SEG1 0 -#define VCE_BASE__INST1_SEG2 0 -#define VCE_BASE__INST1_SEG3 0 -#define VCE_BASE__INST1_SEG4 0 - -#define VCE_BASE__INST2_SEG0 0 -#define VCE_BASE__INST2_SEG1 0 -#define VCE_BASE__INST2_SEG2 0 -#define VCE_BASE__INST2_SEG3 0 -#define VCE_BASE__INST2_SEG4 0 - -#define VCE_BASE__INST3_SEG0 0 -#define VCE_BASE__INST3_SEG1 0 -#define VCE_BASE__INST3_SEG2 0 -#define VCE_BASE__INST3_SEG3 0 -#define VCE_BASE__INST3_SEG4 0 - -#define VCE_BASE__INST4_SEG0 0 -#define VCE_BASE__INST4_SEG1 0 -#define VCE_BASE__INST4_SEG2 0 -#define VCE_BASE__INST4_SEG3 0 -#define VCE_BASE__INST4_SEG4 0 - -#define GC_BASE__INST0_SEG0 0x00002000 -#define GC_BASE__INST0_SEG1 0x0000A000 -#define GC_BASE__INST0_SEG2 0 -#define GC_BASE__INST0_SEG3 0 -#define GC_BASE__INST0_SEG4 0 - -#define GC_BASE__INST1_SEG0 0 -#define GC_BASE__INST1_SEG1 0 -#define GC_BASE__INST1_SEG2 0 -#define GC_BASE__INST1_SEG3 0 -#define GC_BASE__INST1_SEG4 0 - -#define GC_BASE__INST2_SEG0 0 -#define GC_BASE__INST2_SEG1 0 -#define GC_BASE__INST2_SEG2 0 -#define GC_BASE__INST2_SEG3 0 -#define GC_BASE__INST2_SEG4 0 - -#define GC_BASE__INST3_SEG0 0 -#define GC_BASE__INST3_SEG1 0 -#define GC_BASE__INST3_SEG2 0 -#define GC_BASE__INST3_SEG3 0 -#define GC_BASE__INST3_SEG4 0 - -#define GC_BASE__INST4_SEG0 0 -#define GC_BASE__INST4_SEG1 0 -#define GC_BASE__INST4_SEG2 0 -#define GC_BASE__INST4_SEG3 0 -#define GC_BASE__INST4_SEG4 0 - -#define MMHUB_BASE__INST0_SEG0 0x0001A000 -#define MMHUB_BASE__INST0_SEG1 0 -#define MMHUB_BASE__INST0_SEG2 0 -#define MMHUB_BASE__INST0_SEG3 0 -#define MMHUB_BASE__INST0_SEG4 0 - -#define MMHUB_BASE__INST1_SEG0 0 -#define MMHUB_BASE__INST1_SEG1 0 -#define MMHUB_BASE__INST1_SEG2 0 -#define MMHUB_BASE__INST1_SEG3 0 -#define MMHUB_BASE__INST1_SEG4 0 - -#define MMHUB_BASE__INST2_SEG0 0 -#define MMHUB_BASE__INST2_SEG1 0 -#define MMHUB_BASE__INST2_SEG2 0 -#define MMHUB_BASE__INST2_SEG3 0 -#define MMHUB_BASE__INST2_SEG4 0 - -#define MMHUB_BASE__INST3_SEG0 0 -#define MMHUB_BASE__INST3_SEG1 0 -#define MMHUB_BASE__INST3_SEG2 0 -#define MMHUB_BASE__INST3_SEG3 0 -#define MMHUB_BASE__INST3_SEG4 0 - -#define MMHUB_BASE__INST4_SEG0 0 -#define MMHUB_BASE__INST4_SEG1 0 -#define MMHUB_BASE__INST4_SEG2 0 -#define MMHUB_BASE__INST4_SEG3 0 -#define MMHUB_BASE__INST4_SEG4 0 - -#define RSMU_BASE__INST0_SEG0 0x00012000 -#define RSMU_BASE__INST0_SEG1 0 -#define RSMU_BASE__INST0_SEG2 0 -#define RSMU_BASE__INST0_SEG3 0 -#define RSMU_BASE__INST0_SEG4 0 - -#define RSMU_BASE__INST1_SEG0 0 -#define RSMU_BASE__INST1_SEG1 0 -#define RSMU_BASE__INST1_SEG2 0 -#define RSMU_BASE__INST1_SEG3 0 -#define RSMU_BASE__INST1_SEG4 0 - -#define RSMU_BASE__INST2_SEG0 0 -#define RSMU_BASE__INST2_SEG1 0 -#define RSMU_BASE__INST2_SEG2 0 -#define RSMU_BASE__INST2_SEG3 0 -#define RSMU_BASE__INST2_SEG4 0 - -#define RSMU_BASE__INST3_SEG0 0 -#define RSMU_BASE__INST3_SEG1 0 -#define RSMU_BASE__INST3_SEG2 0 -#define RSMU_BASE__INST3_SEG3 0 -#define RSMU_BASE__INST3_SEG4 0 - -#define RSMU_BASE__INST4_SEG0 0 -#define RSMU_BASE__INST4_SEG1 0 -#define RSMU_BASE__INST4_SEG2 0 -#define RSMU_BASE__INST4_SEG3 0 -#define RSMU_BASE__INST4_SEG4 0 - -#define HDP_BASE__INST0_SEG0 0x00000F20 -#define HDP_BASE__INST0_SEG1 0 -#define HDP_BASE__INST0_SEG2 0 -#define HDP_BASE__INST0_SEG3 0 -#define HDP_BASE__INST0_SEG4 0 - -#define HDP_BASE__INST1_SEG0 0 -#define HDP_BASE__INST1_SEG1 0 -#define HDP_BASE__INST1_SEG2 0 -#define HDP_BASE__INST1_SEG3 0 -#define HDP_BASE__INST1_SEG4 0 - -#define HDP_BASE__INST2_SEG0 0 -#define HDP_BASE__INST2_SEG1 0 -#define HDP_BASE__INST2_SEG2 0 -#define HDP_BASE__INST2_SEG3 0 -#define HDP_BASE__INST2_SEG4 0 - -#define HDP_BASE__INST3_SEG0 0 -#define HDP_BASE__INST3_SEG1 0 -#define HDP_BASE__INST3_SEG2 0 -#define HDP_BASE__INST3_SEG3 0 -#define HDP_BASE__INST3_SEG4 0 - -#define HDP_BASE__INST4_SEG0 0 -#define HDP_BASE__INST4_SEG1 0 -#define HDP_BASE__INST4_SEG2 0 -#define HDP_BASE__INST4_SEG3 0 -#define HDP_BASE__INST4_SEG4 0 - -#define OSSSYS_BASE__INST0_SEG0 0x000010A0 -#define OSSSYS_BASE__INST0_SEG1 0 -#define OSSSYS_BASE__INST0_SEG2 0 -#define OSSSYS_BASE__INST0_SEG3 0 -#define OSSSYS_BASE__INST0_SEG4 0 - -#define OSSSYS_BASE__INST1_SEG0 0 -#define OSSSYS_BASE__INST1_SEG1 0 -#define OSSSYS_BASE__INST1_SEG2 0 -#define OSSSYS_BASE__INST1_SEG3 0 -#define OSSSYS_BASE__INST1_SEG4 0 - -#define OSSSYS_BASE__INST2_SEG0 0 -#define OSSSYS_BASE__INST2_SEG1 0 -#define OSSSYS_BASE__INST2_SEG2 0 -#define OSSSYS_BASE__INST2_SEG3 0 -#define OSSSYS_BASE__INST2_SEG4 0 - -#define OSSSYS_BASE__INST3_SEG0 0 -#define OSSSYS_BASE__INST3_SEG1 0 -#define OSSSYS_BASE__INST3_SEG2 0 -#define OSSSYS_BASE__INST3_SEG3 0 -#define OSSSYS_BASE__INST3_SEG4 0 - -#define OSSSYS_BASE__INST4_SEG0 0 -#define OSSSYS_BASE__INST4_SEG1 0 -#define OSSSYS_BASE__INST4_SEG2 0 -#define OSSSYS_BASE__INST4_SEG3 0 -#define OSSSYS_BASE__INST4_SEG4 0 - -#define SDMA0_BASE__INST0_SEG0 0x00001260 -#define SDMA0_BASE__INST0_SEG1 0 -#define SDMA0_BASE__INST0_SEG2 0 -#define SDMA0_BASE__INST0_SEG3 0 -#define SDMA0_BASE__INST0_SEG4 0 - -#define SDMA0_BASE__INST1_SEG0 0 -#define SDMA0_BASE__INST1_SEG1 0 -#define SDMA0_BASE__INST1_SEG2 0 -#define SDMA0_BASE__INST1_SEG3 0 -#define SDMA0_BASE__INST1_SEG4 0 - -#define SDMA0_BASE__INST2_SEG0 0 -#define SDMA0_BASE__INST2_SEG1 0 -#define SDMA0_BASE__INST2_SEG2 0 -#define SDMA0_BASE__INST2_SEG3 0 -#define SDMA0_BASE__INST2_SEG4 0 - -#define SDMA0_BASE__INST3_SEG0 0 -#define SDMA0_BASE__INST3_SEG1 0 -#define SDMA0_BASE__INST3_SEG2 0 -#define SDMA0_BASE__INST3_SEG3 0 -#define SDMA0_BASE__INST3_SEG4 0 - -#define SDMA0_BASE__INST4_SEG0 0 -#define SDMA0_BASE__INST4_SEG1 0 -#define SDMA0_BASE__INST4_SEG2 0 -#define SDMA0_BASE__INST4_SEG3 0 -#define SDMA0_BASE__INST4_SEG4 0 - -#define SDMA1_BASE__INST0_SEG0 0x00001460 -#define SDMA1_BASE__INST0_SEG1 0 -#define SDMA1_BASE__INST0_SEG2 0 -#define SDMA1_BASE__INST0_SEG3 0 -#define SDMA1_BASE__INST0_SEG4 0 - -#define SDMA1_BASE__INST1_SEG0 0 -#define SDMA1_BASE__INST1_SEG1 0 -#define SDMA1_BASE__INST1_SEG2 0 -#define SDMA1_BASE__INST1_SEG3 0 -#define SDMA1_BASE__INST1_SEG4 0 - -#define SDMA1_BASE__INST2_SEG0 0 -#define SDMA1_BASE__INST2_SEG1 0 -#define SDMA1_BASE__INST2_SEG2 0 -#define SDMA1_BASE__INST2_SEG3 0 -#define SDMA1_BASE__INST2_SEG4 0 - -#define SDMA1_BASE__INST3_SEG0 0 -#define SDMA1_BASE__INST3_SEG1 0 -#define SDMA1_BASE__INST3_SEG2 0 -#define SDMA1_BASE__INST3_SEG3 0 -#define SDMA1_BASE__INST3_SEG4 0 - -#define SDMA1_BASE__INST4_SEG0 0 -#define SDMA1_BASE__INST4_SEG1 0 -#define SDMA1_BASE__INST4_SEG2 0 -#define SDMA1_BASE__INST4_SEG3 0 -#define SDMA1_BASE__INST4_SEG4 0 - -#define XDMA_BASE__INST0_SEG0 0x00003400 -#define XDMA_BASE__INST0_SEG1 0 -#define XDMA_BASE__INST0_SEG2 0 -#define XDMA_BASE__INST0_SEG3 0 -#define XDMA_BASE__INST0_SEG4 0 - -#define XDMA_BASE__INST1_SEG0 0 -#define XDMA_BASE__INST1_SEG1 0 -#define XDMA_BASE__INST1_SEG2 0 -#define XDMA_BASE__INST1_SEG3 0 -#define XDMA_BASE__INST1_SEG4 0 - -#define XDMA_BASE__INST2_SEG0 0 -#define XDMA_BASE__INST2_SEG1 0 -#define XDMA_BASE__INST2_SEG2 0 -#define XDMA_BASE__INST2_SEG3 0 -#define XDMA_BASE__INST2_SEG4 0 - -#define XDMA_BASE__INST3_SEG0 0 -#define XDMA_BASE__INST3_SEG1 0 -#define XDMA_BASE__INST3_SEG2 0 -#define XDMA_BASE__INST3_SEG3 0 -#define XDMA_BASE__INST3_SEG4 0 - -#define XDMA_BASE__INST4_SEG0 0 -#define XDMA_BASE__INST4_SEG1 0 -#define XDMA_BASE__INST4_SEG2 0 -#define XDMA_BASE__INST4_SEG3 0 -#define XDMA_BASE__INST4_SEG4 0 - -#define UMC_BASE__INST0_SEG0 0x00014000 -#define UMC_BASE__INST0_SEG1 0 -#define UMC_BASE__INST0_SEG2 0 -#define UMC_BASE__INST0_SEG3 0 -#define UMC_BASE__INST0_SEG4 0 - -#define UMC_BASE__INST1_SEG0 0 -#define UMC_BASE__INST1_SEG1 0 -#define UMC_BASE__INST1_SEG2 0 -#define UMC_BASE__INST1_SEG3 0 -#define UMC_BASE__INST1_SEG4 0 - -#define UMC_BASE__INST2_SEG0 0 -#define UMC_BASE__INST2_SEG1 0 -#define UMC_BASE__INST2_SEG2 0 -#define UMC_BASE__INST2_SEG3 0 -#define UMC_BASE__INST2_SEG4 0 - -#define UMC_BASE__INST3_SEG0 0 -#define UMC_BASE__INST3_SEG1 0 -#define UMC_BASE__INST3_SEG2 0 -#define UMC_BASE__INST3_SEG3 0 -#define UMC_BASE__INST3_SEG4 0 - -#define UMC_BASE__INST4_SEG0 0 -#define UMC_BASE__INST4_SEG1 0 -#define UMC_BASE__INST4_SEG2 0 -#define UMC_BASE__INST4_SEG3 0 -#define UMC_BASE__INST4_SEG4 0 - -#define THM_BASE__INST0_SEG0 0x00016600 -#define THM_BASE__INST0_SEG1 0 -#define THM_BASE__INST0_SEG2 0 -#define THM_BASE__INST0_SEG3 0 -#define THM_BASE__INST0_SEG4 0 - -#define THM_BASE__INST1_SEG0 0 -#define THM_BASE__INST1_SEG1 0 -#define THM_BASE__INST1_SEG2 0 -#define THM_BASE__INST1_SEG3 0 -#define THM_BASE__INST1_SEG4 0 - -#define THM_BASE__INST2_SEG0 0 -#define THM_BASE__INST2_SEG1 0 -#define THM_BASE__INST2_SEG2 0 -#define THM_BASE__INST2_SEG3 0 -#define THM_BASE__INST2_SEG4 0 - -#define THM_BASE__INST3_SEG0 0 -#define THM_BASE__INST3_SEG1 0 -#define THM_BASE__INST3_SEG2 0 -#define THM_BASE__INST3_SEG3 0 -#define THM_BASE__INST3_SEG4 0 - -#define THM_BASE__INST4_SEG0 0 -#define THM_BASE__INST4_SEG1 0 -#define THM_BASE__INST4_SEG2 0 -#define THM_BASE__INST4_SEG3 0 -#define THM_BASE__INST4_SEG4 0 - -#define SMUIO_BASE__INST0_SEG0 0x00016800 -#define SMUIO_BASE__INST0_SEG1 0 -#define SMUIO_BASE__INST0_SEG2 0 -#define SMUIO_BASE__INST0_SEG3 0 -#define SMUIO_BASE__INST0_SEG4 0 - -#define SMUIO_BASE__INST1_SEG0 0 -#define SMUIO_BASE__INST1_SEG1 0 -#define SMUIO_BASE__INST1_SEG2 0 -#define SMUIO_BASE__INST1_SEG3 0 -#define SMUIO_BASE__INST1_SEG4 0 - -#define SMUIO_BASE__INST2_SEG0 0 -#define SMUIO_BASE__INST2_SEG1 0 -#define SMUIO_BASE__INST2_SEG2 0 -#define SMUIO_BASE__INST2_SEG3 0 -#define SMUIO_BASE__INST2_SEG4 0 - -#define SMUIO_BASE__INST3_SEG0 0 -#define SMUIO_BASE__INST3_SEG1 0 -#define SMUIO_BASE__INST3_SEG2 0 -#define SMUIO_BASE__INST3_SEG3 0 -#define SMUIO_BASE__INST3_SEG4 0 - -#define SMUIO_BASE__INST4_SEG0 0 -#define SMUIO_BASE__INST4_SEG1 0 -#define SMUIO_BASE__INST4_SEG2 0 -#define SMUIO_BASE__INST4_SEG3 0 -#define SMUIO_BASE__INST4_SEG4 0 - -#define PWR_BASE__INST0_SEG0 0x00016A00 -#define PWR_BASE__INST0_SEG1 0 -#define PWR_BASE__INST0_SEG2 0 -#define PWR_BASE__INST0_SEG3 0 -#define PWR_BASE__INST0_SEG4 0 - -#define PWR_BASE__INST1_SEG0 0 -#define PWR_BASE__INST1_SEG1 0 -#define PWR_BASE__INST1_SEG2 0 -#define PWR_BASE__INST1_SEG3 0 -#define PWR_BASE__INST1_SEG4 0 - -#define PWR_BASE__INST2_SEG0 0 -#define PWR_BASE__INST2_SEG1 0 -#define PWR_BASE__INST2_SEG2 0 -#define PWR_BASE__INST2_SEG3 0 -#define PWR_BASE__INST2_SEG4 0 - -#define PWR_BASE__INST3_SEG0 0 -#define PWR_BASE__INST3_SEG1 0 -#define PWR_BASE__INST3_SEG2 0 -#define PWR_BASE__INST3_SEG3 0 -#define PWR_BASE__INST3_SEG4 0 - -#define PWR_BASE__INST4_SEG0 0 -#define PWR_BASE__INST4_SEG1 0 -#define PWR_BASE__INST4_SEG2 0 -#define PWR_BASE__INST4_SEG3 0 -#define PWR_BASE__INST4_SEG4 0 - -#define CLK_BASE__INST0_SEG0 0x00016C00 -#define CLK_BASE__INST0_SEG1 0 -#define CLK_BASE__INST0_SEG2 0 -#define CLK_BASE__INST0_SEG3 0 -#define CLK_BASE__INST0_SEG4 0 - -#define CLK_BASE__INST1_SEG0 0x00016E00 -#define CLK_BASE__INST1_SEG1 0 -#define CLK_BASE__INST1_SEG2 0 -#define CLK_BASE__INST1_SEG3 0 -#define CLK_BASE__INST1_SEG4 0 - -#define CLK_BASE__INST2_SEG0 0x00017000 -#define CLK_BASE__INST2_SEG1 0 -#define CLK_BASE__INST2_SEG2 0 -#define CLK_BASE__INST2_SEG3 0 -#define CLK_BASE__INST2_SEG4 0 - -#define CLK_BASE__INST3_SEG0 0x00017200 -#define CLK_BASE__INST3_SEG1 0 -#define CLK_BASE__INST3_SEG2 0 -#define CLK_BASE__INST3_SEG3 0 -#define CLK_BASE__INST3_SEG4 0 - -#define CLK_BASE__INST4_SEG0 0x00017E00 -#define CLK_BASE__INST4_SEG1 0 -#define CLK_BASE__INST4_SEG2 0 -#define CLK_BASE__INST4_SEG3 0 -#define CLK_BASE__INST4_SEG4 0 - -#define FUSE_BASE__INST0_SEG0 0x00017400 -#define FUSE_BASE__INST0_SEG1 0 -#define FUSE_BASE__INST0_SEG2 0 -#define FUSE_BASE__INST0_SEG3 0 -#define FUSE_BASE__INST0_SEG4 0 - -#define FUSE_BASE__INST1_SEG0 0 -#define FUSE_BASE__INST1_SEG1 0 -#define FUSE_BASE__INST1_SEG2 0 -#define FUSE_BASE__INST1_SEG3 0 -#define FUSE_BASE__INST1_SEG4 0 - -#define FUSE_BASE__INST2_SEG0 0 -#define FUSE_BASE__INST2_SEG1 0 -#define FUSE_BASE__INST2_SEG2 0 -#define FUSE_BASE__INST2_SEG3 0 -#define FUSE_BASE__INST2_SEG4 0 - -#define FUSE_BASE__INST3_SEG0 0 -#define FUSE_BASE__INST3_SEG1 0 -#define FUSE_BASE__INST3_SEG2 0 -#define FUSE_BASE__INST3_SEG3 0 -#define FUSE_BASE__INST3_SEG4 0 - -#define FUSE_BASE__INST4_SEG0 0 -#define FUSE_BASE__INST4_SEG1 0 -#define FUSE_BASE__INST4_SEG2 0 -#define FUSE_BASE__INST4_SEG3 0 -#define FUSE_BASE__INST4_SEG4 0 +static const struct IP_BASE NBIF_BASE = {{{{0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE NBIO_BASE = {{{{0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE DCE_BASE = {{{{0x00000012, 0x000000C0, 0x000034C0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE DCN_BASE = {{{{0x00000012, 0x000000C0, 0x000034C0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE MP0_BASE = {{{{0x00016000, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE MP1_BASE = {{{{0x00016000, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE MP2_BASE = {{{{0x00016000, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE DF_BASE = {{{{0x00007000, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE UVD_BASE = {{{{0x00007800, 0x00007E00, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; //note: GLN does not use the first segment +static const struct IP_BASE VCN_BASE = {{{{0x00007800, 0x00007E00, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; //note: GLN does not use the first segment +static const struct IP_BASE DBGU_BASE = {{{{0x00000180, 0x000001A0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; // not exist +static const struct IP_BASE DBGU_NBIO_BASE = {{{{0x000001C0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; // not exist +static const struct IP_BASE DBGU_IO_BASE = {{{{0x000001E0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; // not exist +static const struct IP_BASE DFX_DAP_BASE = {{{{0x000005A0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; // not exist +static const struct IP_BASE DFX_BASE = {{{{0x00000580, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; // this file does not contain registers +static const struct IP_BASE ISP_BASE = {{{{0x00018000, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; // not exist +static const struct IP_BASE SYSTEMHUB_BASE = {{{{0x00000EA0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; // not exist +static const struct IP_BASE L2IMU_BASE = {{{{0x00007DC0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE IOHC_BASE = {{{{0x00010000, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE ATHUB_BASE = {{{{0x00000C20, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE VCE_BASE = {{{{0x00007E00, 0x00048800, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE GC_BASE = {{{{0x00002000, 0x0000A000, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE MMHUB_BASE = {{{{0x0001A000, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE RSMU_BASE = {{{{0x00012000, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE HDP_BASE = {{{{0x00000F20, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE OSSSYS_BASE = {{{{0x000010A0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE SDMA0_BASE = {{{{0x00001260, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE SDMA1_BASE = {{{{0x00001460, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE XDMA_BASE = {{{{0x00003400, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE UMC_BASE = {{{{0x00014000, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE THM_BASE = {{{{0x00016600, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE SMUIO_BASE = {{{{0x00016800, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE PWR_BASE = {{{{0x00016A00, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; +static const struct IP_BASE CLK_BASE = {{{{0x00016C00, 0, 0, 0, 0}}, + {{0x00016E00, 0, 0, 0, 0}}, + {{0x00017000, 0, 0, 0, 0}}, + {{0x00017200, 0, 0, 0, 0}}, + {{0x00017E00, 0, 0, 0, 0}}}}; +static const struct IP_BASE FUSE_BASE = {{{{0x00017400, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}, + {{0, 0, 0, 0, 0}}}}; + +#define NBIF_BASE__INST0_SEG0 0x00000000 +#define NBIF_BASE__INST0_SEG1 0x00000014 +#define NBIF_BASE__INST0_SEG2 0x00000D20 +#define NBIF_BASE__INST0_SEG3 0x00010400 +#define NBIF_BASE__INST0_SEG4 0 + +#define NBIF_BASE__INST1_SEG0 0 +#define NBIF_BASE__INST1_SEG1 0 +#define NBIF_BASE__INST1_SEG2 0 +#define NBIF_BASE__INST1_SEG3 0 +#define NBIF_BASE__INST1_SEG4 0 + +#define NBIF_BASE__INST2_SEG0 0 +#define NBIF_BASE__INST2_SEG1 0 +#define NBIF_BASE__INST2_SEG2 0 +#define NBIF_BASE__INST2_SEG3 0 +#define NBIF_BASE__INST2_SEG4 0 + +#define NBIF_BASE__INST3_SEG0 0 +#define NBIF_BASE__INST3_SEG1 0 +#define NBIF_BASE__INST3_SEG2 0 +#define NBIF_BASE__INST3_SEG3 0 +#define NBIF_BASE__INST3_SEG4 0 + +#define NBIF_BASE__INST4_SEG0 0 +#define NBIF_BASE__INST4_SEG1 0 +#define NBIF_BASE__INST4_SEG2 0 +#define NBIF_BASE__INST4_SEG3 0 +#define NBIF_BASE__INST4_SEG4 0 + +#define NBIO_BASE__INST0_SEG0 0x00000000 +#define NBIO_BASE__INST0_SEG1 0x00000014 +#define NBIO_BASE__INST0_SEG2 0x00000D20 +#define NBIO_BASE__INST0_SEG3 0x00010400 +#define NBIO_BASE__INST0_SEG4 0 + +#define NBIO_BASE__INST1_SEG0 0 +#define NBIO_BASE__INST1_SEG1 0 +#define NBIO_BASE__INST1_SEG2 0 +#define NBIO_BASE__INST1_SEG3 0 +#define NBIO_BASE__INST1_SEG4 0 + +#define NBIO_BASE__INST2_SEG0 0 +#define NBIO_BASE__INST2_SEG1 0 +#define NBIO_BASE__INST2_SEG2 0 +#define NBIO_BASE__INST2_SEG3 0 +#define NBIO_BASE__INST2_SEG4 0 + +#define NBIO_BASE__INST3_SEG0 0 +#define NBIO_BASE__INST3_SEG1 0 +#define NBIO_BASE__INST3_SEG2 0 +#define NBIO_BASE__INST3_SEG3 0 +#define NBIO_BASE__INST3_SEG4 0 + +#define NBIO_BASE__INST4_SEG0 0 +#define NBIO_BASE__INST4_SEG1 0 +#define NBIO_BASE__INST4_SEG2 0 +#define NBIO_BASE__INST4_SEG3 0 +#define NBIO_BASE__INST4_SEG4 0 + +#define DCE_BASE__INST0_SEG0 0x00000012 +#define DCE_BASE__INST0_SEG1 0x000000C0 +#define DCE_BASE__INST0_SEG2 0x000034C0 +#define DCE_BASE__INST0_SEG3 0 +#define DCE_BASE__INST0_SEG4 0 + +#define DCE_BASE__INST1_SEG0 0 +#define DCE_BASE__INST1_SEG1 0 +#define DCE_BASE__INST1_SEG2 0 +#define DCE_BASE__INST1_SEG3 0 +#define DCE_BASE__INST1_SEG4 0 + +#define DCE_BASE__INST2_SEG0 0 +#define DCE_BASE__INST2_SEG1 0 +#define DCE_BASE__INST2_SEG2 0 +#define DCE_BASE__INST2_SEG3 0 +#define DCE_BASE__INST2_SEG4 0 + +#define DCE_BASE__INST3_SEG0 0 +#define DCE_BASE__INST3_SEG1 0 +#define DCE_BASE__INST3_SEG2 0 +#define DCE_BASE__INST3_SEG3 0 +#define DCE_BASE__INST3_SEG4 0 + +#define DCE_BASE__INST4_SEG0 0 +#define DCE_BASE__INST4_SEG1 0 +#define DCE_BASE__INST4_SEG2 0 +#define DCE_BASE__INST4_SEG3 0 +#define DCE_BASE__INST4_SEG4 0 + +#define DCN_BASE__INST0_SEG0 0x00000012 +#define DCN_BASE__INST0_SEG1 0x000000C0 +#define DCN_BASE__INST0_SEG2 0x000034C0 +#define DCN_BASE__INST0_SEG3 0 +#define DCN_BASE__INST0_SEG4 0 + +#define DCN_BASE__INST1_SEG0 0 +#define DCN_BASE__INST1_SEG1 0 +#define DCN_BASE__INST1_SEG2 0 +#define DCN_BASE__INST1_SEG3 0 +#define DCN_BASE__INST1_SEG4 0 + +#define DCN_BASE__INST2_SEG0 0 +#define DCN_BASE__INST2_SEG1 0 +#define DCN_BASE__INST2_SEG2 0 +#define DCN_BASE__INST2_SEG3 0 +#define DCN_BASE__INST2_SEG4 0 + +#define DCN_BASE__INST3_SEG0 0 +#define DCN_BASE__INST3_SEG1 0 +#define DCN_BASE__INST3_SEG2 0 +#define DCN_BASE__INST3_SEG3 0 +#define DCN_BASE__INST3_SEG4 0 + +#define DCN_BASE__INST4_SEG0 0 +#define DCN_BASE__INST4_SEG1 0 +#define DCN_BASE__INST4_SEG2 0 +#define DCN_BASE__INST4_SEG3 0 +#define DCN_BASE__INST4_SEG4 0 + +#define MP0_BASE__INST0_SEG0 0x00016000 +#define MP0_BASE__INST0_SEG1 0 +#define MP0_BASE__INST0_SEG2 0 +#define MP0_BASE__INST0_SEG3 0 +#define MP0_BASE__INST0_SEG4 0 + +#define MP0_BASE__INST1_SEG0 0 +#define MP0_BASE__INST1_SEG1 0 +#define MP0_BASE__INST1_SEG2 0 +#define MP0_BASE__INST1_SEG3 0 +#define MP0_BASE__INST1_SEG4 0 + +#define MP0_BASE__INST2_SEG0 0 +#define MP0_BASE__INST2_SEG1 0 +#define MP0_BASE__INST2_SEG2 0 +#define MP0_BASE__INST2_SEG3 0 +#define MP0_BASE__INST2_SEG4 0 + +#define MP0_BASE__INST3_SEG0 0 +#define MP0_BASE__INST3_SEG1 0 +#define MP0_BASE__INST3_SEG2 0 +#define MP0_BASE__INST3_SEG3 0 +#define MP0_BASE__INST3_SEG4 0 + +#define MP0_BASE__INST4_SEG0 0 +#define MP0_BASE__INST4_SEG1 0 +#define MP0_BASE__INST4_SEG2 0 +#define MP0_BASE__INST4_SEG3 0 +#define MP0_BASE__INST4_SEG4 0 + +#define MP1_BASE__INST0_SEG0 0x00016200 +#define MP1_BASE__INST0_SEG1 0 +#define MP1_BASE__INST0_SEG2 0 +#define MP1_BASE__INST0_SEG3 0 +#define MP1_BASE__INST0_SEG4 0 + +#define MP1_BASE__INST1_SEG0 0 +#define MP1_BASE__INST1_SEG1 0 +#define MP1_BASE__INST1_SEG2 0 +#define MP1_BASE__INST1_SEG3 0 +#define MP1_BASE__INST1_SEG4 0 + +#define MP1_BASE__INST2_SEG0 0 +#define MP1_BASE__INST2_SEG1 0 +#define MP1_BASE__INST2_SEG2 0 +#define MP1_BASE__INST2_SEG3 0 +#define MP1_BASE__INST2_SEG4 0 + +#define MP1_BASE__INST3_SEG0 0 +#define MP1_BASE__INST3_SEG1 0 +#define MP1_BASE__INST3_SEG2 0 +#define MP1_BASE__INST3_SEG3 0 +#define MP1_BASE__INST3_SEG4 0 + +#define MP1_BASE__INST4_SEG0 0 +#define MP1_BASE__INST4_SEG1 0 +#define MP1_BASE__INST4_SEG2 0 +#define MP1_BASE__INST4_SEG3 0 +#define MP1_BASE__INST4_SEG4 0 + +#define MP2_BASE__INST0_SEG0 0x00016400 +#define MP2_BASE__INST0_SEG1 0 +#define MP2_BASE__INST0_SEG2 0 +#define MP2_BASE__INST0_SEG3 0 +#define MP2_BASE__INST0_SEG4 0 + +#define MP2_BASE__INST1_SEG0 0 +#define MP2_BASE__INST1_SEG1 0 +#define MP2_BASE__INST1_SEG2 0 +#define MP2_BASE__INST1_SEG3 0 +#define MP2_BASE__INST1_SEG4 0 + +#define MP2_BASE__INST2_SEG0 0 +#define MP2_BASE__INST2_SEG1 0 +#define MP2_BASE__INST2_SEG2 0 +#define MP2_BASE__INST2_SEG3 0 +#define MP2_BASE__INST2_SEG4 0 + +#define MP2_BASE__INST3_SEG0 0 +#define MP2_BASE__INST3_SEG1 0 +#define MP2_BASE__INST3_SEG2 0 +#define MP2_BASE__INST3_SEG3 0 +#define MP2_BASE__INST3_SEG4 0 + +#define MP2_BASE__INST4_SEG0 0 +#define MP2_BASE__INST4_SEG1 0 +#define MP2_BASE__INST4_SEG2 0 +#define MP2_BASE__INST4_SEG3 0 +#define MP2_BASE__INST4_SEG4 0 + +#define DF_BASE__INST0_SEG0 0x00007000 +#define DF_BASE__INST0_SEG1 0 +#define DF_BASE__INST0_SEG2 0 +#define DF_BASE__INST0_SEG3 0 +#define DF_BASE__INST0_SEG4 0 + +#define DF_BASE__INST1_SEG0 0 +#define DF_BASE__INST1_SEG1 0 +#define DF_BASE__INST1_SEG2 0 +#define DF_BASE__INST1_SEG3 0 +#define DF_BASE__INST1_SEG4 0 + +#define DF_BASE__INST2_SEG0 0 +#define DF_BASE__INST2_SEG1 0 +#define DF_BASE__INST2_SEG2 0 +#define DF_BASE__INST2_SEG3 0 +#define DF_BASE__INST2_SEG4 0 + +#define DF_BASE__INST3_SEG0 0 +#define DF_BASE__INST3_SEG1 0 +#define DF_BASE__INST3_SEG2 0 +#define DF_BASE__INST3_SEG3 0 +#define DF_BASE__INST3_SEG4 0 + +#define DF_BASE__INST4_SEG0 0 +#define DF_BASE__INST4_SEG1 0 +#define DF_BASE__INST4_SEG2 0 +#define DF_BASE__INST4_SEG3 0 +#define DF_BASE__INST4_SEG4 0 + +#define UVD_BASE__INST0_SEG0 0x00007800 +#define UVD_BASE__INST0_SEG1 0x00007E00 +#define UVD_BASE__INST0_SEG2 0 +#define UVD_BASE__INST0_SEG3 0 +#define UVD_BASE__INST0_SEG4 0 + +#define UVD_BASE__INST1_SEG0 0 +#define UVD_BASE__INST1_SEG1 0 +#define UVD_BASE__INST1_SEG2 0 +#define UVD_BASE__INST1_SEG3 0 +#define UVD_BASE__INST1_SEG4 0 + +#define UVD_BASE__INST2_SEG0 0 +#define UVD_BASE__INST2_SEG1 0 +#define UVD_BASE__INST2_SEG2 0 +#define UVD_BASE__INST2_SEG3 0 +#define UVD_BASE__INST2_SEG4 0 + +#define UVD_BASE__INST3_SEG0 0 +#define UVD_BASE__INST3_SEG1 0 +#define UVD_BASE__INST3_SEG2 0 +#define UVD_BASE__INST3_SEG3 0 +#define UVD_BASE__INST3_SEG4 0 + +#define UVD_BASE__INST4_SEG0 0 +#define UVD_BASE__INST4_SEG1 0 +#define UVD_BASE__INST4_SEG2 0 +#define UVD_BASE__INST4_SEG3 0 +#define UVD_BASE__INST4_SEG4 0 + +#define VCN_BASE__INST0_SEG0 0x00007800 +#define VCN_BASE__INST0_SEG1 0x00007E00 +#define VCN_BASE__INST0_SEG2 0 +#define VCN_BASE__INST0_SEG3 0 +#define VCN_BASE__INST0_SEG4 0 + +#define VCN_BASE__INST1_SEG0 0 +#define VCN_BASE__INST1_SEG1 0 +#define VCN_BASE__INST1_SEG2 0 +#define VCN_BASE__INST1_SEG3 0 +#define VCN_BASE__INST1_SEG4 0 + +#define VCN_BASE__INST2_SEG0 0 +#define VCN_BASE__INST2_SEG1 0 +#define VCN_BASE__INST2_SEG2 0 +#define VCN_BASE__INST2_SEG3 0 +#define VCN_BASE__INST2_SEG4 0 + +#define VCN_BASE__INST3_SEG0 0 +#define VCN_BASE__INST3_SEG1 0 +#define VCN_BASE__INST3_SEG2 0 +#define VCN_BASE__INST3_SEG3 0 +#define VCN_BASE__INST3_SEG4 0 + +#define VCN_BASE__INST4_SEG0 0 +#define VCN_BASE__INST4_SEG1 0 +#define VCN_BASE__INST4_SEG2 0 +#define VCN_BASE__INST4_SEG3 0 +#define VCN_BASE__INST4_SEG4 0 + +#define DBGU_BASE__INST0_SEG0 0x00000180 +#define DBGU_BASE__INST0_SEG1 0x000001A0 +#define DBGU_BASE__INST0_SEG2 0 +#define DBGU_BASE__INST0_SEG3 0 +#define DBGU_BASE__INST0_SEG4 0 + +#define DBGU_BASE__INST1_SEG0 0 +#define DBGU_BASE__INST1_SEG1 0 +#define DBGU_BASE__INST1_SEG2 0 +#define DBGU_BASE__INST1_SEG3 0 +#define DBGU_BASE__INST1_SEG4 0 + +#define DBGU_BASE__INST2_SEG0 0 +#define DBGU_BASE__INST2_SEG1 0 +#define DBGU_BASE__INST2_SEG2 0 +#define DBGU_BASE__INST2_SEG3 0 +#define DBGU_BASE__INST2_SEG4 0 + +#define DBGU_BASE__INST3_SEG0 0 +#define DBGU_BASE__INST3_SEG1 0 +#define DBGU_BASE__INST3_SEG2 0 +#define DBGU_BASE__INST3_SEG3 0 +#define DBGU_BASE__INST3_SEG4 0 + +#define DBGU_BASE__INST4_SEG0 0 +#define DBGU_BASE__INST4_SEG1 0 +#define DBGU_BASE__INST4_SEG2 0 +#define DBGU_BASE__INST4_SEG3 0 +#define DBGU_BASE__INST4_SEG4 0 + +#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0 +#define DBGU_NBIO_BASE__INST0_SEG1 0 +#define DBGU_NBIO_BASE__INST0_SEG2 0 +#define DBGU_NBIO_BASE__INST0_SEG3 0 +#define DBGU_NBIO_BASE__INST0_SEG4 0 + +#define DBGU_NBIO_BASE__INST1_SEG0 0 +#define DBGU_NBIO_BASE__INST1_SEG1 0 +#define DBGU_NBIO_BASE__INST1_SEG2 0 +#define DBGU_NBIO_BASE__INST1_SEG3 0 +#define DBGU_NBIO_BASE__INST1_SEG4 0 + +#define DBGU_NBIO_BASE__INST2_SEG0 0 +#define DBGU_NBIO_BASE__INST2_SEG1 0 +#define DBGU_NBIO_BASE__INST2_SEG2 0 +#define DBGU_NBIO_BASE__INST2_SEG3 0 +#define DBGU_NBIO_BASE__INST2_SEG4 0 + +#define DBGU_NBIO_BASE__INST3_SEG0 0 +#define DBGU_NBIO_BASE__INST3_SEG1 0 +#define DBGU_NBIO_BASE__INST3_SEG2 0 +#define DBGU_NBIO_BASE__INST3_SEG3 0 +#define DBGU_NBIO_BASE__INST3_SEG4 0 + +#define DBGU_NBIO_BASE__INST4_SEG0 0 +#define DBGU_NBIO_BASE__INST4_SEG1 0 +#define DBGU_NBIO_BASE__INST4_SEG2 0 +#define DBGU_NBIO_BASE__INST4_SEG3 0 +#define DBGU_NBIO_BASE__INST4_SEG4 0 + +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0 +#define DBGU_IO_BASE__INST0_SEG1 0 +#define DBGU_IO_BASE__INST0_SEG2 0 +#define DBGU_IO_BASE__INST0_SEG3 0 +#define DBGU_IO_BASE__INST0_SEG4 0 + +#define DBGU_IO_BASE__INST1_SEG0 0 +#define DBGU_IO_BASE__INST1_SEG1 0 +#define DBGU_IO_BASE__INST1_SEG2 0 +#define DBGU_IO_BASE__INST1_SEG3 0 +#define DBGU_IO_BASE__INST1_SEG4 0 + +#define DBGU_IO_BASE__INST2_SEG0 0 +#define DBGU_IO_BASE__INST2_SEG1 0 +#define DBGU_IO_BASE__INST2_SEG2 0 +#define DBGU_IO_BASE__INST2_SEG3 0 +#define DBGU_IO_BASE__INST2_SEG4 0 + +#define DBGU_IO_BASE__INST3_SEG0 0 +#define DBGU_IO_BASE__INST3_SEG1 0 +#define DBGU_IO_BASE__INST3_SEG2 0 +#define DBGU_IO_BASE__INST3_SEG3 0 +#define DBGU_IO_BASE__INST3_SEG4 0 + +#define DBGU_IO_BASE__INST4_SEG0 0 +#define DBGU_IO_BASE__INST4_SEG1 0 +#define DBGU_IO_BASE__INST4_SEG2 0 +#define DBGU_IO_BASE__INST4_SEG3 0 +#define DBGU_IO_BASE__INST4_SEG4 0 + +#define DFX_DAP_BASE__INST0_SEG0 0x000005A0 +#define DFX_DAP_BASE__INST0_SEG1 0 +#define DFX_DAP_BASE__INST0_SEG2 0 +#define DFX_DAP_BASE__INST0_SEG3 0 +#define DFX_DAP_BASE__INST0_SEG4 0 + +#define DFX_DAP_BASE__INST1_SEG0 0 +#define DFX_DAP_BASE__INST1_SEG1 0 +#define DFX_DAP_BASE__INST1_SEG2 0 +#define DFX_DAP_BASE__INST1_SEG3 0 +#define DFX_DAP_BASE__INST1_SEG4 0 + +#define DFX_DAP_BASE__INST2_SEG0 0 +#define DFX_DAP_BASE__INST2_SEG1 0 +#define DFX_DAP_BASE__INST2_SEG2 0 +#define DFX_DAP_BASE__INST2_SEG3 0 +#define DFX_DAP_BASE__INST2_SEG4 0 + +#define DFX_DAP_BASE__INST3_SEG0 0 +#define DFX_DAP_BASE__INST3_SEG1 0 +#define DFX_DAP_BASE__INST3_SEG2 0 +#define DFX_DAP_BASE__INST3_SEG3 0 +#define DFX_DAP_BASE__INST3_SEG4 0 + +#define DFX_DAP_BASE__INST4_SEG0 0 +#define DFX_DAP_BASE__INST4_SEG1 0 +#define DFX_DAP_BASE__INST4_SEG2 0 +#define DFX_DAP_BASE__INST4_SEG3 0 +#define DFX_DAP_BASE__INST4_SEG4 0 + +#define DFX_BASE__INST0_SEG0 0x00000580 +#define DFX_BASE__INST0_SEG1 0 +#define DFX_BASE__INST0_SEG2 0 +#define DFX_BASE__INST0_SEG3 0 +#define DFX_BASE__INST0_SEG4 0 + +#define DFX_BASE__INST1_SEG0 0 +#define DFX_BASE__INST1_SEG1 0 +#define DFX_BASE__INST1_SEG2 0 +#define DFX_BASE__INST1_SEG3 0 +#define DFX_BASE__INST1_SEG4 0 + +#define DFX_BASE__INST2_SEG0 0 +#define DFX_BASE__INST2_SEG1 0 +#define DFX_BASE__INST2_SEG2 0 +#define DFX_BASE__INST2_SEG3 0 +#define DFX_BASE__INST2_SEG4 0 + +#define DFX_BASE__INST3_SEG0 0 +#define DFX_BASE__INST3_SEG1 0 +#define DFX_BASE__INST3_SEG2 0 +#define DFX_BASE__INST3_SEG3 0 +#define DFX_BASE__INST3_SEG4 0 + +#define DFX_BASE__INST4_SEG0 0 +#define DFX_BASE__INST4_SEG1 0 +#define DFX_BASE__INST4_SEG2 0 +#define DFX_BASE__INST4_SEG3 0 +#define DFX_BASE__INST4_SEG4 0 + +#define ISP_BASE__INST0_SEG0 0x00018000 +#define ISP_BASE__INST0_SEG1 0 +#define ISP_BASE__INST0_SEG2 0 +#define ISP_BASE__INST0_SEG3 0 +#define ISP_BASE__INST0_SEG4 0 + +#define ISP_BASE__INST1_SEG0 0 +#define ISP_BASE__INST1_SEG1 0 +#define ISP_BASE__INST1_SEG2 0 +#define ISP_BASE__INST1_SEG3 0 +#define ISP_BASE__INST1_SEG4 0 + +#define ISP_BASE__INST2_SEG0 0 +#define ISP_BASE__INST2_SEG1 0 +#define ISP_BASE__INST2_SEG2 0 +#define ISP_BASE__INST2_SEG3 0 +#define ISP_BASE__INST2_SEG4 0 + +#define ISP_BASE__INST3_SEG0 0 +#define ISP_BASE__INST3_SEG1 0 +#define ISP_BASE__INST3_SEG2 0 +#define ISP_BASE__INST3_SEG3 0 +#define ISP_BASE__INST3_SEG4 0 + +#define ISP_BASE__INST4_SEG0 0 +#define ISP_BASE__INST4_SEG1 0 +#define ISP_BASE__INST4_SEG2 0 +#define ISP_BASE__INST4_SEG3 0 +#define ISP_BASE__INST4_SEG4 0 + +#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0 +#define SYSTEMHUB_BASE__INST0_SEG1 0 +#define SYSTEMHUB_BASE__INST0_SEG2 0 +#define SYSTEMHUB_BASE__INST0_SEG3 0 +#define SYSTEMHUB_BASE__INST0_SEG4 0 + +#define SYSTEMHUB_BASE__INST1_SEG0 0 +#define SYSTEMHUB_BASE__INST1_SEG1 0 +#define SYSTEMHUB_BASE__INST1_SEG2 0 +#define SYSTEMHUB_BASE__INST1_SEG3 0 +#define SYSTEMHUB_BASE__INST1_SEG4 0 + +#define SYSTEMHUB_BASE__INST2_SEG0 0 +#define SYSTEMHUB_BASE__INST2_SEG1 0 +#define SYSTEMHUB_BASE__INST2_SEG2 0 +#define SYSTEMHUB_BASE__INST2_SEG3 0 +#define SYSTEMHUB_BASE__INST2_SEG4 0 + +#define SYSTEMHUB_BASE__INST3_SEG0 0 +#define SYSTEMHUB_BASE__INST3_SEG1 0 +#define SYSTEMHUB_BASE__INST3_SEG2 0 +#define SYSTEMHUB_BASE__INST3_SEG3 0 +#define SYSTEMHUB_BASE__INST3_SEG4 0 + +#define SYSTEMHUB_BASE__INST4_SEG0 0 +#define SYSTEMHUB_BASE__INST4_SEG1 0 +#define SYSTEMHUB_BASE__INST4_SEG2 0 +#define SYSTEMHUB_BASE__INST4_SEG3 0 +#define SYSTEMHUB_BASE__INST4_SEG4 0 + +#define L2IMU_BASE__INST0_SEG0 0x00007DC0 +#define L2IMU_BASE__INST0_SEG1 0 +#define L2IMU_BASE__INST0_SEG2 0 +#define L2IMU_BASE__INST0_SEG3 0 +#define L2IMU_BASE__INST0_SEG4 0 + +#define L2IMU_BASE__INST1_SEG0 0 +#define L2IMU_BASE__INST1_SEG1 0 +#define L2IMU_BASE__INST1_SEG2 0 +#define L2IMU_BASE__INST1_SEG3 0 +#define L2IMU_BASE__INST1_SEG4 0 + +#define L2IMU_BASE__INST2_SEG0 0 +#define L2IMU_BASE__INST2_SEG1 0 +#define L2IMU_BASE__INST2_SEG2 0 +#define L2IMU_BASE__INST2_SEG3 0 +#define L2IMU_BASE__INST2_SEG4 0 + +#define L2IMU_BASE__INST3_SEG0 0 +#define L2IMU_BASE__INST3_SEG1 0 +#define L2IMU_BASE__INST3_SEG2 0 +#define L2IMU_BASE__INST3_SEG3 0 +#define L2IMU_BASE__INST3_SEG4 0 + +#define L2IMU_BASE__INST4_SEG0 0 +#define L2IMU_BASE__INST4_SEG1 0 +#define L2IMU_BASE__INST4_SEG2 0 +#define L2IMU_BASE__INST4_SEG3 0 +#define L2IMU_BASE__INST4_SEG4 0 + +#define IOHC_BASE__INST0_SEG0 0x00010000 +#define IOHC_BASE__INST0_SEG1 0 +#define IOHC_BASE__INST0_SEG2 0 +#define IOHC_BASE__INST0_SEG3 0 +#define IOHC_BASE__INST0_SEG4 0 + +#define IOHC_BASE__INST1_SEG0 0 +#define IOHC_BASE__INST1_SEG1 0 +#define IOHC_BASE__INST1_SEG2 0 +#define IOHC_BASE__INST1_SEG3 0 +#define IOHC_BASE__INST1_SEG4 0 + +#define IOHC_BASE__INST2_SEG0 0 +#define IOHC_BASE__INST2_SEG1 0 +#define IOHC_BASE__INST2_SEG2 0 +#define IOHC_BASE__INST2_SEG3 0 +#define IOHC_BASE__INST2_SEG4 0 + +#define IOHC_BASE__INST3_SEG0 0 +#define IOHC_BASE__INST3_SEG1 0 +#define IOHC_BASE__INST3_SEG2 0 +#define IOHC_BASE__INST3_SEG3 0 +#define IOHC_BASE__INST3_SEG4 0 + +#define IOHC_BASE__INST4_SEG0 0 +#define IOHC_BASE__INST4_SEG1 0 +#define IOHC_BASE__INST4_SEG2 0 +#define IOHC_BASE__INST4_SEG3 0 +#define IOHC_BASE__INST4_SEG4 0 + +#define ATHUB_BASE__INST0_SEG0 0x00000C20 +#define ATHUB_BASE__INST0_SEG1 0 +#define ATHUB_BASE__INST0_SEG2 0 +#define ATHUB_BASE__INST0_SEG3 0 +#define ATHUB_BASE__INST0_SEG4 0 + +#define ATHUB_BASE__INST1_SEG0 0 +#define ATHUB_BASE__INST1_SEG1 0 +#define ATHUB_BASE__INST1_SEG2 0 +#define ATHUB_BASE__INST1_SEG3 0 +#define ATHUB_BASE__INST1_SEG4 0 + +#define ATHUB_BASE__INST2_SEG0 0 +#define ATHUB_BASE__INST2_SEG1 0 +#define ATHUB_BASE__INST2_SEG2 0 +#define ATHUB_BASE__INST2_SEG3 0 +#define ATHUB_BASE__INST2_SEG4 0 + +#define ATHUB_BASE__INST3_SEG0 0 +#define ATHUB_BASE__INST3_SEG1 0 +#define ATHUB_BASE__INST3_SEG2 0 +#define ATHUB_BASE__INST3_SEG3 0 +#define ATHUB_BASE__INST3_SEG4 0 + +#define ATHUB_BASE__INST4_SEG0 0 +#define ATHUB_BASE__INST4_SEG1 0 +#define ATHUB_BASE__INST4_SEG2 0 +#define ATHUB_BASE__INST4_SEG3 0 +#define ATHUB_BASE__INST4_SEG4 0 + +#define VCE_BASE__INST0_SEG0 0x00007E00 +#define VCE_BASE__INST0_SEG1 0x00048800 +#define VCE_BASE__INST0_SEG2 0 +#define VCE_BASE__INST0_SEG3 0 +#define VCE_BASE__INST0_SEG4 0 + +#define VCE_BASE__INST1_SEG0 0 +#define VCE_BASE__INST1_SEG1 0 +#define VCE_BASE__INST1_SEG2 0 +#define VCE_BASE__INST1_SEG3 0 +#define VCE_BASE__INST1_SEG4 0 + +#define VCE_BASE__INST2_SEG0 0 +#define VCE_BASE__INST2_SEG1 0 +#define VCE_BASE__INST2_SEG2 0 +#define VCE_BASE__INST2_SEG3 0 +#define VCE_BASE__INST2_SEG4 0 + +#define VCE_BASE__INST3_SEG0 0 +#define VCE_BASE__INST3_SEG1 0 +#define VCE_BASE__INST3_SEG2 0 +#define VCE_BASE__INST3_SEG3 0 +#define VCE_BASE__INST3_SEG4 0 + +#define VCE_BASE__INST4_SEG0 0 +#define VCE_BASE__INST4_SEG1 0 +#define VCE_BASE__INST4_SEG2 0 +#define VCE_BASE__INST4_SEG3 0 +#define VCE_BASE__INST4_SEG4 0 + +#define GC_BASE__INST0_SEG0 0x00002000 +#define GC_BASE__INST0_SEG1 0x0000A000 +#define GC_BASE__INST0_SEG2 0 +#define GC_BASE__INST0_SEG3 0 +#define GC_BASE__INST0_SEG4 0 + +#define GC_BASE__INST1_SEG0 0 +#define GC_BASE__INST1_SEG1 0 +#define GC_BASE__INST1_SEG2 0 +#define GC_BASE__INST1_SEG3 0 +#define GC_BASE__INST1_SEG4 0 + +#define GC_BASE__INST2_SEG0 0 +#define GC_BASE__INST2_SEG1 0 +#define GC_BASE__INST2_SEG2 0 +#define GC_BASE__INST2_SEG3 0 +#define GC_BASE__INST2_SEG4 0 + +#define GC_BASE__INST3_SEG0 0 +#define GC_BASE__INST3_SEG1 0 +#define GC_BASE__INST3_SEG2 0 +#define GC_BASE__INST3_SEG3 0 +#define GC_BASE__INST3_SEG4 0 + +#define GC_BASE__INST4_SEG0 0 +#define GC_BASE__INST4_SEG1 0 +#define GC_BASE__INST4_SEG2 0 +#define GC_BASE__INST4_SEG3 0 +#define GC_BASE__INST4_SEG4 0 + +#define MMHUB_BASE__INST0_SEG0 0x0001A000 +#define MMHUB_BASE__INST0_SEG1 0 +#define MMHUB_BASE__INST0_SEG2 0 +#define MMHUB_BASE__INST0_SEG3 0 +#define MMHUB_BASE__INST0_SEG4 0 + +#define MMHUB_BASE__INST1_SEG0 0 +#define MMHUB_BASE__INST1_SEG1 0 +#define MMHUB_BASE__INST1_SEG2 0 +#define MMHUB_BASE__INST1_SEG3 0 +#define MMHUB_BASE__INST1_SEG4 0 + +#define MMHUB_BASE__INST2_SEG0 0 +#define MMHUB_BASE__INST2_SEG1 0 +#define MMHUB_BASE__INST2_SEG2 0 +#define MMHUB_BASE__INST2_SEG3 0 +#define MMHUB_BASE__INST2_SEG4 0 + +#define MMHUB_BASE__INST3_SEG0 0 +#define MMHUB_BASE__INST3_SEG1 0 +#define MMHUB_BASE__INST3_SEG2 0 +#define MMHUB_BASE__INST3_SEG3 0 +#define MMHUB_BASE__INST3_SEG4 0 + +#define MMHUB_BASE__INST4_SEG0 0 +#define MMHUB_BASE__INST4_SEG1 0 +#define MMHUB_BASE__INST4_SEG2 0 +#define MMHUB_BASE__INST4_SEG3 0 +#define MMHUB_BASE__INST4_SEG4 0 + +#define RSMU_BASE__INST0_SEG0 0x00012000 +#define RSMU_BASE__INST0_SEG1 0 +#define RSMU_BASE__INST0_SEG2 0 +#define RSMU_BASE__INST0_SEG3 0 +#define RSMU_BASE__INST0_SEG4 0 + +#define RSMU_BASE__INST1_SEG0 0 +#define RSMU_BASE__INST1_SEG1 0 +#define RSMU_BASE__INST1_SEG2 0 +#define RSMU_BASE__INST1_SEG3 0 +#define RSMU_BASE__INST1_SEG4 0 + +#define RSMU_BASE__INST2_SEG0 0 +#define RSMU_BASE__INST2_SEG1 0 +#define RSMU_BASE__INST2_SEG2 0 +#define RSMU_BASE__INST2_SEG3 0 +#define RSMU_BASE__INST2_SEG4 0 + +#define RSMU_BASE__INST3_SEG0 0 +#define RSMU_BASE__INST3_SEG1 0 +#define RSMU_BASE__INST3_SEG2 0 +#define RSMU_BASE__INST3_SEG3 0 +#define RSMU_BASE__INST3_SEG4 0 + +#define RSMU_BASE__INST4_SEG0 0 +#define RSMU_BASE__INST4_SEG1 0 +#define RSMU_BASE__INST4_SEG2 0 +#define RSMU_BASE__INST4_SEG3 0 +#define RSMU_BASE__INST4_SEG4 0 + +#define HDP_BASE__INST0_SEG0 0x00000F20 +#define HDP_BASE__INST0_SEG1 0 +#define HDP_BASE__INST0_SEG2 0 +#define HDP_BASE__INST0_SEG3 0 +#define HDP_BASE__INST0_SEG4 0 + +#define HDP_BASE__INST1_SEG0 0 +#define HDP_BASE__INST1_SEG1 0 +#define HDP_BASE__INST1_SEG2 0 +#define HDP_BASE__INST1_SEG3 0 +#define HDP_BASE__INST1_SEG4 0 + +#define HDP_BASE__INST2_SEG0 0 +#define HDP_BASE__INST2_SEG1 0 +#define HDP_BASE__INST2_SEG2 0 +#define HDP_BASE__INST2_SEG3 0 +#define HDP_BASE__INST2_SEG4 0 + +#define HDP_BASE__INST3_SEG0 0 +#define HDP_BASE__INST3_SEG1 0 +#define HDP_BASE__INST3_SEG2 0 +#define HDP_BASE__INST3_SEG3 0 +#define HDP_BASE__INST3_SEG4 0 + +#define HDP_BASE__INST4_SEG0 0 +#define HDP_BASE__INST4_SEG1 0 +#define HDP_BASE__INST4_SEG2 0 +#define HDP_BASE__INST4_SEG3 0 +#define HDP_BASE__INST4_SEG4 0 + +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 +#define OSSSYS_BASE__INST0_SEG1 0 +#define OSSSYS_BASE__INST0_SEG2 0 +#define OSSSYS_BASE__INST0_SEG3 0 +#define OSSSYS_BASE__INST0_SEG4 0 + +#define OSSSYS_BASE__INST1_SEG0 0 +#define OSSSYS_BASE__INST1_SEG1 0 +#define OSSSYS_BASE__INST1_SEG2 0 +#define OSSSYS_BASE__INST1_SEG3 0 +#define OSSSYS_BASE__INST1_SEG4 0 + +#define OSSSYS_BASE__INST2_SEG0 0 +#define OSSSYS_BASE__INST2_SEG1 0 +#define OSSSYS_BASE__INST2_SEG2 0 +#define OSSSYS_BASE__INST2_SEG3 0 +#define OSSSYS_BASE__INST2_SEG4 0 + +#define OSSSYS_BASE__INST3_SEG0 0 +#define OSSSYS_BASE__INST3_SEG1 0 +#define OSSSYS_BASE__INST3_SEG2 0 +#define OSSSYS_BASE__INST3_SEG3 0 +#define OSSSYS_BASE__INST3_SEG4 0 + +#define OSSSYS_BASE__INST4_SEG0 0 +#define OSSSYS_BASE__INST4_SEG1 0 +#define OSSSYS_BASE__INST4_SEG2 0 +#define OSSSYS_BASE__INST4_SEG3 0 +#define OSSSYS_BASE__INST4_SEG4 0 + +#define SDMA0_BASE__INST0_SEG0 0x00001260 +#define SDMA0_BASE__INST0_SEG1 0 +#define SDMA0_BASE__INST0_SEG2 0 +#define SDMA0_BASE__INST0_SEG3 0 +#define SDMA0_BASE__INST0_SEG4 0 + +#define SDMA0_BASE__INST1_SEG0 0 +#define SDMA0_BASE__INST1_SEG1 0 +#define SDMA0_BASE__INST1_SEG2 0 +#define SDMA0_BASE__INST1_SEG3 0 +#define SDMA0_BASE__INST1_SEG4 0 + +#define SDMA0_BASE__INST2_SEG0 0 +#define SDMA0_BASE__INST2_SEG1 0 +#define SDMA0_BASE__INST2_SEG2 0 +#define SDMA0_BASE__INST2_SEG3 0 +#define SDMA0_BASE__INST2_SEG4 0 + +#define SDMA0_BASE__INST3_SEG0 0 +#define SDMA0_BASE__INST3_SEG1 0 +#define SDMA0_BASE__INST3_SEG2 0 +#define SDMA0_BASE__INST3_SEG3 0 +#define SDMA0_BASE__INST3_SEG4 0 + +#define SDMA0_BASE__INST4_SEG0 0 +#define SDMA0_BASE__INST4_SEG1 0 +#define SDMA0_BASE__INST4_SEG2 0 +#define SDMA0_BASE__INST4_SEG3 0 +#define SDMA0_BASE__INST4_SEG4 0 + +#define SDMA1_BASE__INST0_SEG0 0x00001460 +#define SDMA1_BASE__INST0_SEG1 0 +#define SDMA1_BASE__INST0_SEG2 0 +#define SDMA1_BASE__INST0_SEG3 0 +#define SDMA1_BASE__INST0_SEG4 0 + +#define SDMA1_BASE__INST1_SEG0 0 +#define SDMA1_BASE__INST1_SEG1 0 +#define SDMA1_BASE__INST1_SEG2 0 +#define SDMA1_BASE__INST1_SEG3 0 +#define SDMA1_BASE__INST1_SEG4 0 + +#define SDMA1_BASE__INST2_SEG0 0 +#define SDMA1_BASE__INST2_SEG1 0 +#define SDMA1_BASE__INST2_SEG2 0 +#define SDMA1_BASE__INST2_SEG3 0 +#define SDMA1_BASE__INST2_SEG4 0 + +#define SDMA1_BASE__INST3_SEG0 0 +#define SDMA1_BASE__INST3_SEG1 0 +#define SDMA1_BASE__INST3_SEG2 0 +#define SDMA1_BASE__INST3_SEG3 0 +#define SDMA1_BASE__INST3_SEG4 0 + +#define SDMA1_BASE__INST4_SEG0 0 +#define SDMA1_BASE__INST4_SEG1 0 +#define SDMA1_BASE__INST4_SEG2 0 +#define SDMA1_BASE__INST4_SEG3 0 +#define SDMA1_BASE__INST4_SEG4 0 + +#define XDMA_BASE__INST0_SEG0 0x00003400 +#define XDMA_BASE__INST0_SEG1 0 +#define XDMA_BASE__INST0_SEG2 0 +#define XDMA_BASE__INST0_SEG3 0 +#define XDMA_BASE__INST0_SEG4 0 + +#define XDMA_BASE__INST1_SEG0 0 +#define XDMA_BASE__INST1_SEG1 0 +#define XDMA_BASE__INST1_SEG2 0 +#define XDMA_BASE__INST1_SEG3 0 +#define XDMA_BASE__INST1_SEG4 0 + +#define XDMA_BASE__INST2_SEG0 0 +#define XDMA_BASE__INST2_SEG1 0 +#define XDMA_BASE__INST2_SEG2 0 +#define XDMA_BASE__INST2_SEG3 0 +#define XDMA_BASE__INST2_SEG4 0 + +#define XDMA_BASE__INST3_SEG0 0 +#define XDMA_BASE__INST3_SEG1 0 +#define XDMA_BASE__INST3_SEG2 0 +#define XDMA_BASE__INST3_SEG3 0 +#define XDMA_BASE__INST3_SEG4 0 + +#define XDMA_BASE__INST4_SEG0 0 +#define XDMA_BASE__INST4_SEG1 0 +#define XDMA_BASE__INST4_SEG2 0 +#define XDMA_BASE__INST4_SEG3 0 +#define XDMA_BASE__INST4_SEG4 0 + +#define UMC_BASE__INST0_SEG0 0x00014000 +#define UMC_BASE__INST0_SEG1 0 +#define UMC_BASE__INST0_SEG2 0 +#define UMC_BASE__INST0_SEG3 0 +#define UMC_BASE__INST0_SEG4 0 + +#define UMC_BASE__INST1_SEG0 0 +#define UMC_BASE__INST1_SEG1 0 +#define UMC_BASE__INST1_SEG2 0 +#define UMC_BASE__INST1_SEG3 0 +#define UMC_BASE__INST1_SEG4 0 + +#define UMC_BASE__INST2_SEG0 0 +#define UMC_BASE__INST2_SEG1 0 +#define UMC_BASE__INST2_SEG2 0 +#define UMC_BASE__INST2_SEG3 0 +#define UMC_BASE__INST2_SEG4 0 + +#define UMC_BASE__INST3_SEG0 0 +#define UMC_BASE__INST3_SEG1 0 +#define UMC_BASE__INST3_SEG2 0 +#define UMC_BASE__INST3_SEG3 0 +#define UMC_BASE__INST3_SEG4 0 + +#define UMC_BASE__INST4_SEG0 0 +#define UMC_BASE__INST4_SEG1 0 +#define UMC_BASE__INST4_SEG2 0 +#define UMC_BASE__INST4_SEG3 0 +#define UMC_BASE__INST4_SEG4 0 + +#define THM_BASE__INST0_SEG0 0x00016600 +#define THM_BASE__INST0_SEG1 0 +#define THM_BASE__INST0_SEG2 0 +#define THM_BASE__INST0_SEG3 0 +#define THM_BASE__INST0_SEG4 0 + +#define THM_BASE__INST1_SEG0 0 +#define THM_BASE__INST1_SEG1 0 +#define THM_BASE__INST1_SEG2 0 +#define THM_BASE__INST1_SEG3 0 +#define THM_BASE__INST1_SEG4 0 + +#define THM_BASE__INST2_SEG0 0 +#define THM_BASE__INST2_SEG1 0 +#define THM_BASE__INST2_SEG2 0 +#define THM_BASE__INST2_SEG3 0 +#define THM_BASE__INST2_SEG4 0 + +#define THM_BASE__INST3_SEG0 0 +#define THM_BASE__INST3_SEG1 0 +#define THM_BASE__INST3_SEG2 0 +#define THM_BASE__INST3_SEG3 0 +#define THM_BASE__INST3_SEG4 0 + +#define THM_BASE__INST4_SEG0 0 +#define THM_BASE__INST4_SEG1 0 +#define THM_BASE__INST4_SEG2 0 +#define THM_BASE__INST4_SEG3 0 +#define THM_BASE__INST4_SEG4 0 + +#define SMUIO_BASE__INST0_SEG0 0x00016800 +#define SMUIO_BASE__INST0_SEG1 0 +#define SMUIO_BASE__INST0_SEG2 0 +#define SMUIO_BASE__INST0_SEG3 0 +#define SMUIO_BASE__INST0_SEG4 0 + +#define SMUIO_BASE__INST1_SEG0 0 +#define SMUIO_BASE__INST1_SEG1 0 +#define SMUIO_BASE__INST1_SEG2 0 +#define SMUIO_BASE__INST1_SEG3 0 +#define SMUIO_BASE__INST1_SEG4 0 + +#define SMUIO_BASE__INST2_SEG0 0 +#define SMUIO_BASE__INST2_SEG1 0 +#define SMUIO_BASE__INST2_SEG2 0 +#define SMUIO_BASE__INST2_SEG3 0 +#define SMUIO_BASE__INST2_SEG4 0 + +#define SMUIO_BASE__INST3_SEG0 0 +#define SMUIO_BASE__INST3_SEG1 0 +#define SMUIO_BASE__INST3_SEG2 0 +#define SMUIO_BASE__INST3_SEG3 0 +#define SMUIO_BASE__INST3_SEG4 0 + +#define SMUIO_BASE__INST4_SEG0 0 +#define SMUIO_BASE__INST4_SEG1 0 +#define SMUIO_BASE__INST4_SEG2 0 +#define SMUIO_BASE__INST4_SEG3 0 +#define SMUIO_BASE__INST4_SEG4 0 + +#define PWR_BASE__INST0_SEG0 0x00016A00 +#define PWR_BASE__INST0_SEG1 0 +#define PWR_BASE__INST0_SEG2 0 +#define PWR_BASE__INST0_SEG3 0 +#define PWR_BASE__INST0_SEG4 0 + +#define PWR_BASE__INST1_SEG0 0 +#define PWR_BASE__INST1_SEG1 0 +#define PWR_BASE__INST1_SEG2 0 +#define PWR_BASE__INST1_SEG3 0 +#define PWR_BASE__INST1_SEG4 0 + +#define PWR_BASE__INST2_SEG0 0 +#define PWR_BASE__INST2_SEG1 0 +#define PWR_BASE__INST2_SEG2 0 +#define PWR_BASE__INST2_SEG3 0 +#define PWR_BASE__INST2_SEG4 0 + +#define PWR_BASE__INST3_SEG0 0 +#define PWR_BASE__INST3_SEG1 0 +#define PWR_BASE__INST3_SEG2 0 +#define PWR_BASE__INST3_SEG3 0 +#define PWR_BASE__INST3_SEG4 0 + +#define PWR_BASE__INST4_SEG0 0 +#define PWR_BASE__INST4_SEG1 0 +#define PWR_BASE__INST4_SEG2 0 +#define PWR_BASE__INST4_SEG3 0 +#define PWR_BASE__INST4_SEG4 0 + +#define CLK_BASE__INST0_SEG0 0x00016C00 +#define CLK_BASE__INST0_SEG1 0 +#define CLK_BASE__INST0_SEG2 0 +#define CLK_BASE__INST0_SEG3 0 +#define CLK_BASE__INST0_SEG4 0 + +#define CLK_BASE__INST1_SEG0 0x00016E00 +#define CLK_BASE__INST1_SEG1 0 +#define CLK_BASE__INST1_SEG2 0 +#define CLK_BASE__INST1_SEG3 0 +#define CLK_BASE__INST1_SEG4 0 + +#define CLK_BASE__INST2_SEG0 0x00017000 +#define CLK_BASE__INST2_SEG1 0 +#define CLK_BASE__INST2_SEG2 0 +#define CLK_BASE__INST2_SEG3 0 +#define CLK_BASE__INST2_SEG4 0 + +#define CLK_BASE__INST3_SEG0 0x00017200 +#define CLK_BASE__INST3_SEG1 0 +#define CLK_BASE__INST3_SEG2 0 +#define CLK_BASE__INST3_SEG3 0 +#define CLK_BASE__INST3_SEG4 0 + +#define CLK_BASE__INST4_SEG0 0x00017E00 +#define CLK_BASE__INST4_SEG1 0 +#define CLK_BASE__INST4_SEG2 0 +#define CLK_BASE__INST4_SEG3 0 +#define CLK_BASE__INST4_SEG4 0 + +#define FUSE_BASE__INST0_SEG0 0x00017400 +#define FUSE_BASE__INST0_SEG1 0 +#define FUSE_BASE__INST0_SEG2 0 +#define FUSE_BASE__INST0_SEG3 0 +#define FUSE_BASE__INST0_SEG4 0 + +#define FUSE_BASE__INST1_SEG0 0 +#define FUSE_BASE__INST1_SEG1 0 +#define FUSE_BASE__INST1_SEG2 0 +#define FUSE_BASE__INST1_SEG3 0 +#define FUSE_BASE__INST1_SEG4 0 + +#define FUSE_BASE__INST2_SEG0 0 +#define FUSE_BASE__INST2_SEG1 0 +#define FUSE_BASE__INST2_SEG2 0 +#define FUSE_BASE__INST2_SEG3 0 +#define FUSE_BASE__INST2_SEG4 0 + +#define FUSE_BASE__INST3_SEG0 0 +#define FUSE_BASE__INST3_SEG1 0 +#define FUSE_BASE__INST3_SEG2 0 +#define FUSE_BASE__INST3_SEG3 0 +#define FUSE_BASE__INST3_SEG4 0 + +#define FUSE_BASE__INST4_SEG0 0 +#define FUSE_BASE__INST4_SEG1 0 +#define FUSE_BASE__INST4_SEG2 0 +#define FUSE_BASE__INST4_SEG3 0 +#define FUSE_BASE__INST4_SEG4 0 #endif - diff --git a/src/amd/amdgpu/navi12_reg_init.c b/src/amd/amdgpu/navi12_reg_init.c new file mode 100644 index 0000000..daa28ac --- /dev/null +++ b/src/amd/amdgpu/navi12_reg_init.c @@ -0,0 +1,53 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "compat.h" +#include "nv.h" + +#include "soc15_common.h" +#include "navi12_ip_offset.h" + +int navi12_reg_base_init(struct amd_fake_dev *adev) +{ + /* HW has more IP blocks, only initialized the blocks needed by driver */ + uint32_t i; + for (i = 0; i < MAX_INSTANCE; ++i) + { + adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); + adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); + adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); + adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); + adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); + adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); + adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i])); + adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); + adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i])); + adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); + adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); + adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); + adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); + } + return 0; +} diff --git a/src/amd/amdgpu/navi14_reg_init.c b/src/amd/amdgpu/navi14_reg_init.c new file mode 100644 index 0000000..4f890ff --- /dev/null +++ b/src/amd/amdgpu/navi14_reg_init.c @@ -0,0 +1,54 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "compat.h" +#include "nv.h" + +#include "soc15_common.h" +#include "navi14_ip_offset.h" + +int navi14_reg_base_init(struct amd_fake_dev *adev) +{ + int i; + + for (i = 0; i < MAX_INSTANCE; ++i) + { + adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); + adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); + adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); + adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); + adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); + adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); + adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i])); + adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); + adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i])); + adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); + adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); + adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); + adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); + } + + return 0; +} diff --git a/src/amd/common.c b/src/amd/common.c index 6d5171f..c1a46aa 100644 --- a/src/amd/common.c +++ b/src/amd/common.c @@ -25,6 +25,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA #include "soc15_common.h" #include "soc15.h" #include "common.h" +#include "compat.h" int amd_common_pre_reset(struct vendor_reset_dev *dev) { @@ -98,7 +99,7 @@ int amd_common_post_reset(struct vendor_reset_dev *dev) return 0; } -static int smu_wait(struct amd_fake_dev *adev) +int smu_wait(struct amd_fake_dev *adev) { u32 ret; int timeout; @@ -152,4 +153,44 @@ out: int smum_send_msg_to_smc(struct amd_fake_dev *adev, uint16_t msg, uint32_t *resp) { return smum_send_msg_to_smc_with_parameter(adev, msg, 0, resp); +} + +/* from amdgpu_atombios.c */ +void amdgpu_atombios_scratch_regs_engine_hung(struct amd_fake_dev *adev, + bool hung) +{ + u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3); + + if (hung) + tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; + else + tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; + + WREG32(adev->bios_scratch_reg_offset + 3, tmp); +} + +/* from amdgpu_psp.c */ +int psp_wait_for(struct amd_fake_dev *adev, uint32_t reg_index, + uint32_t reg_val, uint32_t mask, bool check_changed) +{ + uint32_t val; + int i; + + for (i = 0; i < 100000; i++) + { + val = RREG32(reg_index); + if (check_changed) + { + if (val != reg_val) + return 0; + } + else + { + if ((val & mask) == reg_val) + return 0; + } + udelay(1); + } + + return -ETIME; } \ No newline at end of file diff --git a/src/amd/common.h b/src/amd/common.h index 7f8f487..deab8f8 100644 --- a/src/amd/common.h +++ b/src/amd/common.h @@ -144,6 +144,12 @@ int amd_common_pre_reset(struct vendor_reset_dev *); int amd_common_post_reset(struct vendor_reset_dev *); int smum_send_msg_to_smc(struct amd_fake_dev *adev, uint16_t msg, uint32_t *resp); -int smum_send_msg_to_smc_with_parameter(struct amd_fake_dev *adev, uint16_t msg, uint32_t parameter, uint32_t *resp); +int smum_send_msg_to_smc_with_parameter(struct amd_fake_dev *adev, uint16_t msg, + uint32_t parameter, uint32_t *resp); + +void amdgpu_atombios_scratch_regs_engine_hung(struct amd_fake_dev *adev, bool hung); + +int smu_wait(struct amd_fake_dev *adev); +int psp_wait_for(struct amd_fake_dev *adev, uint32_t reg_index, uint32_t reg_val, uint32_t mask, bool check_changed); #endif diff --git a/src/amd/navi10.c b/src/amd/navi10.c index e347e39..c201316 100644 --- a/src/amd/navi10.c +++ b/src/amd/navi10.c @@ -17,20 +17,34 @@ this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +#include + #include "vendor-reset-dev.h" +#include "amd.h" #include "common.h" #include "firmware.h" #include "amdgpu_discovery.h" +#include "smu_v11_0.h" +#include "mp/mp_11_0_offset.h" +#include "mp/mp_11_0_sh_mask.h" +#include "nbio_2_3_offset.h" +#include "psp_gfx_if.h" #include "nv.h" +#define log_prefix "Navi10/12/14: " +#define nv_info(fmt, arg...) pci_info(dev->pdev, log_prefix fmt, ##arg) +#define nv_warn(fmt, arg...) pci_warn(dev->pdev, log_prefix fmt, ##arg) +#define nv_err(fmt, arg...) pci_err(dev->pdev, log_prefix fmt, ##arg) + extern bool amdgpu_get_bios(struct amd_fake_dev *adev); static int amd_navi10_reset(struct vendor_reset_dev *dev) { struct amd_vendor_private *priv = amd_private(dev); struct amd_fake_dev *adev; - int ret; + int ret = 0, timeout; + u32 sol, smu_resp, mp1_intr, psp_bl_ready, tmp, offset; adev = &priv->adev; ret = amd_fake_dev_init(adev, dev); @@ -40,26 +54,208 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev) ret = amdgpu_discovery_reg_base_init(adev); if (ret < 0) { - pci_info(dev->pdev, - "amdgpu_discovery_reg_base_init failed, using legacy method\n"); - navi10_reg_base_init(adev); + nv_info("amdgpu_discovery_reg_base_init failed, using legacy method\n"); + switch (dev->info) + { + case AMD_NAVI10: + navi10_reg_base_init(adev); + break; + case AMD_NAVI12: + navi12_reg_base_init(adev); + break; + case AMD_NAVI14: + navi14_reg_base_init(adev); + break; + default: + pci_err(dev->pdev, "Unknown Navi type device: [%04x:%04x]\n", dev->pdev->vendor, dev->pdev->device); + return -ENOTSUPP; + } } if (!amdgpu_get_bios(adev)) { - pci_err(dev->pdev, "amdgpu_get_bios failed: %d\n", ret); + nv_err("amdgpu_get_bios failed: %d\n", ret); ret = -ENOTSUPP; - goto adev_free; + goto free_adev; } ret = atom_bios_init(adev); if (ret) { - pci_err(dev->pdev, "atom_bios_init failed: %d\n", ret); - goto adev_free; + nv_err("atom_bios_init failed: %d\n", ret); + goto free_adev; + } + + /* it's important we wait for the SOC to be ready */ + for (timeout = 100000; timeout; --timeout) + { + sol = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); + if (sol != 0xFFFFFFFF && sol != 0) + break; + udelay(1); + } + + if (sol == ~1L) + { + nv_warn("Timed out waiting for SOL to be valid\n"); + /* continuing anyway because sometimes it can still be reset from here */ + } + + nv_info("bus reset disabled? %s\n", (dev->pdev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) ? "yes" : "no"); + + /* collect some info for logging for now */ + smu_resp = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); + mp1_intr = (RREG32_PCIE(MP1_Public | + (smnMP1_FIRMWARE_FLAGS & 0xffffffff)) & + MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> + MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT; + psp_bl_ready = !!(RREG32(mmMP0_SMN_C2PMSG_35) & 0x80000000L); + nv_info("SMU response reg: %x, sol reg: %x, mp1 intr enabled? %s, bl ready? %s\n", + smu_resp, sol, mp1_intr ? "yes" : "no", + psp_bl_ready ? "yes" : "no"); + + /* okay, if we're in this state, we're probably reset */ + if (sol == 0x0 && !mp1_intr && psp_bl_ready) + goto free_adev; + + /* this tells the drivers nvram is lost and everything needs to be reset */ + nv_info("Clearing scratch regs 6 and 7\n"); + WREG32(adev->bios_scratch_reg_offset + 6, 0); + WREG32(adev->bios_scratch_reg_offset + 7, 0); + + /* it only makes sense to reset mp1 if it's running + * XXX: is this even necessary? in early testing, I ran into + * situations where MP1 was alive but not responsive, but in + * later testing I have not been able to replicate this scenario. + */ + if (smu_resp != 0x01 && mp1_intr) + { + nv_info("MP1 reset\n"); + WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), + 1 & MP1_SMN_PUB_CTRL__RESET_MASK); + WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), + 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK); + + nv_info("wait for MP1\n"); + for (timeout = 100000; timeout; --timeout) + { + tmp = RREG32_PCIE(MP1_Public | + (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); + if ((tmp & + MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> + MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) + break; + udelay(1); + } + + if (!timeout && + !((tmp & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> + MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)) + { + nv_warn("timed out waiting for MP1 reset\n"); + } + + smu_wait(adev); + smu_resp = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); + nv_info("SMU resp reg: %x\n", tmp); + } + + /* + * again, this only makes sense if we have an SMU to talk to + * some of these may fail, that's okay. we're just turning off as many + * things as possible + */ + if (mp1_intr) + { + smu_wait(adev); + + /* disallowgfx_off or something */ + nv_info("gfx off\n"); + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0x00); + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, 0x00); + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, 0x2A); + smu_wait(adev); + + /* stop SMC */ + nv_info("Prep Reset\n"); + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0x00); + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, 0x00); + /* PPSMC_MSG_PrepareMp1ForReset */ + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, 0x33); + smu_wait(adev); + } + + nv_info("begin psp mode 1 reset\n"); + amdgpu_atombios_scratch_regs_engine_hung(adev, true); + + pci_save_state(dev->pdev); + + /* check validity of PSP before reset */ + nv_info("PSP wait\n"); + offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); + tmp = psp_wait_for(adev, offset, 0x80000000, 0x8000FFFF, false); + if (tmp) + nv_warn("timed out waiting for PSP to reach valid state, but continuing anyway\n"); + + /* reset command */ + nv_info("do mode1 reset\n"); + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_MODE1_RST); + msleep(500); + + /* wait for ACK */ + nv_info("PSP wait\n"); + offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); + tmp = psp_wait_for(adev, offset, 0x80000000, 0x80000000, false); + if (tmp) + { + nv_warn("PSP did not acknowledger reset\n"); + ret = -EINVAL; + goto out; } -adev_free: + nv_info("mode1 reset succeeded\n"); + + pci_restore_state(dev->pdev); + + for (timeout = 100000; timeout; --timeout) + { + tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); + + if (tmp != 0xffffffff) + break; + udelay(1); + } + nv_info("memsize: %x\n", tmp); + + /* + * this takes a long time :( + */ + for (timeout = 100; timeout; --timeout) + { + /* see if PSP bootloader comes back */ + if (RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L) + break; + + nv_info("PSP bootloader flags? %x, timeout: %s\n", + RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35), !timeout ? "yes" : "no"); + + msleep(100); + } + + if (!timeout && !(RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L)) + { + nv_warn("timed out waiting for PSP bootloader to respond after reset\n"); + ret = -ETIME; + } + else + nv_info("PSP mode1 reset successful\n"); + + pci_restore_state(dev->pdev); + +out: + amdgpu_atombios_scratch_regs_engine_hung(adev, false); + +free_adev: amd_fake_dev_fini(adev); return ret; diff --git a/src/amd/polaris10.c b/src/amd/polaris10.c index 7831fcd..39dc18f 100644 --- a/src/amd/polaris10.c +++ b/src/amd/polaris10.c @@ -25,7 +25,6 @@ Place, Suite 330, Boston, MA 02111-1307 USA #include "common.h" #include "compat.h" -#define bios_scratch_reg_offset mmBIOS_SCRATCH_0 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b /* from amdgpu.h */ /* from vi.c */ @@ -52,20 +51,6 @@ static int vi_gpu_pci_config_reset(struct amd_fake_dev *adev) return -EINVAL; } -static inline void amdgpu_atombios_scratch_regs_engine_hung(struct amd_fake_dev *adev, bool hung) -{ - u32 tmp; - - tmp = RREG32(bios_scratch_reg_offset + 3); - - if (hung) - tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; - else - tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; - - WREG32(bios_scratch_reg_offset + 3, tmp); -} - static int amd_polaris10_reset(struct vendor_reset_dev *vdev) { int ret = 0; @@ -76,6 +61,9 @@ static int amd_polaris10_reset(struct vendor_reset_dev *vdev) if (ret) return ret; + /* pre-firmware constant */ + adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0; + amdgpu_atombios_scratch_regs_engine_hung(adev, true); ret = vi_gpu_pci_config_reset(adev); amdgpu_atombios_scratch_regs_engine_hung(adev, false); diff --git a/src/amd/vega10.c b/src/amd/vega10.c index b3b8086..85bdcc8 100644 --- a/src/amd/vega10.c +++ b/src/amd/vega10.c @@ -126,7 +126,7 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev) { struct amd_vendor_private *priv = amd_private(dev); struct amd_fake_dev *adev; - int ret, timeout; + int ret = 0, timeout; u32 sol, smu_resp, mp1_intr, psp_bl_ready; enum BACO_STATE baco_state; @@ -168,12 +168,13 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev) if (sol == ~1L && baco_state != BACO_STATE_IN) { pci_warn(dev->pdev, "Vega10: Timed out waiting for SOL to be valid\n"); - return -EINVAL; + ret = -EINVAL; + goto free_adev; } /* if there's no sign of life we usually can't reset */ if (!sol) - return 0; + goto free_adev; if (baco_state == BACO_STATE_OUT) { diff --git a/src/device-db.h b/src/device-db.h index e07ee0a..e02d903 100644 --- a/src/device-db.h +++ b/src/device-db.h @@ -18,91 +18,96 @@ Place, Suite 330, Boston, MA 02111-1307 USA #include "amd/amd.h" -#define AMD_POLARIS10(op) \ - {PCI_VENDOR_ID_ATI, 0x67C0, op}, \ - {PCI_VENDOR_ID_ATI, 0x67C1, op}, \ - {PCI_VENDOR_ID_ATI, 0x67C2, op}, \ - {PCI_VENDOR_ID_ATI, 0x67C4, op}, \ - {PCI_VENDOR_ID_ATI, 0x67C7, op}, \ - {PCI_VENDOR_ID_ATI, 0x67D0, op}, \ - {PCI_VENDOR_ID_ATI, 0x67DF, op}, \ - {PCI_VENDOR_ID_ATI, 0x67C8, op}, \ - {PCI_VENDOR_ID_ATI, 0x67C9, op}, \ - {PCI_VENDOR_ID_ATI, 0x67CA, op}, \ - {PCI_VENDOR_ID_ATI, 0x67CC, op}, \ - {PCI_VENDOR_ID_ATI, 0x67CF, op}, \ - {PCI_VENDOR_ID_ATI, 0x6FDF, op} +#define _AMD_POLARIS10(op) \ + {PCI_VENDOR_ID_ATI, 0x67C0, op, AMD_POLARIS10}, \ + {PCI_VENDOR_ID_ATI, 0x67C1, op, AMD_POLARIS10}, \ + {PCI_VENDOR_ID_ATI, 0x67C2, op, AMD_POLARIS10}, \ + {PCI_VENDOR_ID_ATI, 0x67C4, op, AMD_POLARIS10}, \ + {PCI_VENDOR_ID_ATI, 0x67C7, op, AMD_POLARIS10}, \ + {PCI_VENDOR_ID_ATI, 0x67D0, op, AMD_POLARIS10}, \ + {PCI_VENDOR_ID_ATI, 0x67DF, op, AMD_POLARIS10}, \ + {PCI_VENDOR_ID_ATI, 0x67C8, op, AMD_POLARIS10}, \ + {PCI_VENDOR_ID_ATI, 0x67C9, op, AMD_POLARIS10}, \ + {PCI_VENDOR_ID_ATI, 0x67CA, op, AMD_POLARIS10}, \ + {PCI_VENDOR_ID_ATI, 0x67CC, op, AMD_POLARIS10}, \ + {PCI_VENDOR_ID_ATI, 0x67CF, op, AMD_POLARIS10}, \ + {PCI_VENDOR_ID_ATI, 0x6FDF, op, AMD_POLARIS10} -#define AMD_POLARIS11(op) \ - {PCI_VENDOR_ID_ATI, 0x67E0, op}, \ - {PCI_VENDOR_ID_ATI, 0x67E3, op}, \ - {PCI_VENDOR_ID_ATI, 0x67E8, op}, \ - {PCI_VENDOR_ID_ATI, 0x67EB, op}, \ - {PCI_VENDOR_ID_ATI, 0x67EF, op}, \ - {PCI_VENDOR_ID_ATI, 0x67FF, op}, \ - {PCI_VENDOR_ID_ATI, 0x67E1, op}, \ - {PCI_VENDOR_ID_ATI, 0x67E7, op}, \ - {PCI_VENDOR_ID_ATI, 0x67E9, op} +#define _AMD_POLARIS11(op) \ + {PCI_VENDOR_ID_ATI, 0x67E0, op, AMD_POLARIS11}, \ + {PCI_VENDOR_ID_ATI, 0x67E3, op, AMD_POLARIS11}, \ + {PCI_VENDOR_ID_ATI, 0x67E8, op, AMD_POLARIS11}, \ + {PCI_VENDOR_ID_ATI, 0x67EB, op, AMD_POLARIS11}, \ + {PCI_VENDOR_ID_ATI, 0x67EF, op, AMD_POLARIS11}, \ + {PCI_VENDOR_ID_ATI, 0x67FF, op, AMD_POLARIS11}, \ + {PCI_VENDOR_ID_ATI, 0x67E1, op, AMD_POLARIS11}, \ + {PCI_VENDOR_ID_ATI, 0x67E7, op, AMD_POLARIS11}, \ + {PCI_VENDOR_ID_ATI, 0x67E9, op, AMD_POLARIS11} -#define AMD_POLARIS12(op) \ - {PCI_VENDOR_ID_ATI, 0x6980, op}, \ - {PCI_VENDOR_ID_ATI, 0x6981, op}, \ - {PCI_VENDOR_ID_ATI, 0x6985, op}, \ - {PCI_VENDOR_ID_ATI, 0x6986, op}, \ - {PCI_VENDOR_ID_ATI, 0x6987, op}, \ - {PCI_VENDOR_ID_ATI, 0x6995, op}, \ - {PCI_VENDOR_ID_ATI, 0x6997, op}, \ - {PCI_VENDOR_ID_ATI, 0x699F, op} +#define _AMD_POLARIS12(op) \ + {PCI_VENDOR_ID_ATI, 0x6980, op, AMD_POLARIS12}, \ + {PCI_VENDOR_ID_ATI, 0x6981, op, AMD_POLARIS12}, \ + {PCI_VENDOR_ID_ATI, 0x6985, op, AMD_POLARIS12}, \ + {PCI_VENDOR_ID_ATI, 0x6986, op, AMD_POLARIS12}, \ + {PCI_VENDOR_ID_ATI, 0x6987, op, AMD_POLARIS12}, \ + {PCI_VENDOR_ID_ATI, 0x6995, op, AMD_POLARIS12}, \ + {PCI_VENDOR_ID_ATI, 0x6997, op, AMD_POLARIS12}, \ + {PCI_VENDOR_ID_ATI, 0x699F, op, AMD_POLARIS12} -#define AMD_VEGA10(op) \ - {PCI_VENDOR_ID_ATI, 0x6860, op}, \ - {PCI_VENDOR_ID_ATI, 0x6861, op}, \ - {PCI_VENDOR_ID_ATI, 0x6862, op}, \ - {PCI_VENDOR_ID_ATI, 0x6863, op}, \ - {PCI_VENDOR_ID_ATI, 0x6864, op}, \ - {PCI_VENDOR_ID_ATI, 0x6867, op}, \ - {PCI_VENDOR_ID_ATI, 0x6868, op}, \ - {PCI_VENDOR_ID_ATI, 0x6869, op}, \ - {PCI_VENDOR_ID_ATI, 0x686a, op}, \ - {PCI_VENDOR_ID_ATI, 0x686b, op}, \ - {PCI_VENDOR_ID_ATI, 0x686c, op}, \ - {PCI_VENDOR_ID_ATI, 0x686d, op}, \ - {PCI_VENDOR_ID_ATI, 0x686e, op}, \ - {PCI_VENDOR_ID_ATI, 0x686f, op}, \ - {PCI_VENDOR_ID_ATI, 0x687f, op} +#define _AMD_VEGA10(op) \ + {PCI_VENDOR_ID_ATI, 0x6860, op, AMD_VEGA10}, \ + {PCI_VENDOR_ID_ATI, 0x6861, op, AMD_VEGA10}, \ + {PCI_VENDOR_ID_ATI, 0x6862, op, AMD_VEGA10}, \ + {PCI_VENDOR_ID_ATI, 0x6863, op, AMD_VEGA10}, \ + {PCI_VENDOR_ID_ATI, 0x6864, op, AMD_VEGA10}, \ + {PCI_VENDOR_ID_ATI, 0x6867, op, AMD_VEGA10}, \ + {PCI_VENDOR_ID_ATI, 0x6868, op, AMD_VEGA10}, \ + {PCI_VENDOR_ID_ATI, 0x6869, op, AMD_VEGA10}, \ + {PCI_VENDOR_ID_ATI, 0x686a, op, AMD_VEGA10}, \ + {PCI_VENDOR_ID_ATI, 0x686b, op, AMD_VEGA10}, \ + {PCI_VENDOR_ID_ATI, 0x686c, op, AMD_VEGA10}, \ + {PCI_VENDOR_ID_ATI, 0x686d, op, AMD_VEGA10}, \ + {PCI_VENDOR_ID_ATI, 0x686e, op, AMD_VEGA10}, \ + {PCI_VENDOR_ID_ATI, 0x686f, op, AMD_VEGA10}, \ + {PCI_VENDOR_ID_ATI, 0x687f, op, AMD_VEGA10} -#define AMD_VEGA20(op) \ - {PCI_VENDOR_ID_ATI, 0x66a0, op}, \ - {PCI_VENDOR_ID_ATI, 0x66a1, op}, \ - {PCI_VENDOR_ID_ATI, 0x66a2, op}, \ - {PCI_VENDOR_ID_ATI, 0x66a3, op}, \ - {PCI_VENDOR_ID_ATI, 0x66a4, op}, \ - {PCI_VENDOR_ID_ATI, 0x66a7, op}, \ - {PCI_VENDOR_ID_ATI, 0x66af, op} +#define _AMD_VEGA20(op) \ + {PCI_VENDOR_ID_ATI, 0x66a0, op, AMD_VEGA20}, \ + {PCI_VENDOR_ID_ATI, 0x66a1, op, AMD_VEGA20}, \ + {PCI_VENDOR_ID_ATI, 0x66a2, op, AMD_VEGA20}, \ + {PCI_VENDOR_ID_ATI, 0x66a3, op, AMD_VEGA20}, \ + {PCI_VENDOR_ID_ATI, 0x66a4, op, AMD_VEGA20}, \ + {PCI_VENDOR_ID_ATI, 0x66a7, op, AMD_VEGA20}, \ + {PCI_VENDOR_ID_ATI, 0x66af, op, AMD_VEGA20} -#define AMD_NAVI10(op) \ - {PCI_VENDOR_ID_ATI, 0x7310, op}, \ - {PCI_VENDOR_ID_ATI, 0x7312, op}, \ - {PCI_VENDOR_ID_ATI, 0x7318, op}, \ - {PCI_VENDOR_ID_ATI, 0x7319, op}, \ - {PCI_VENDOR_ID_ATI, 0x731a, op}, \ - {PCI_VENDOR_ID_ATI, 0x731b, op}, \ - {PCI_VENDOR_ID_ATI, 0x731e, op}, \ - {PCI_VENDOR_ID_ATI, 0x731f, op} +#define _AMD_NAVI10(op) \ + {PCI_VENDOR_ID_ATI, 0x7310, op, AMD_NAVI10}, \ + {PCI_VENDOR_ID_ATI, 0x7312, op, AMD_NAVI10}, \ + {PCI_VENDOR_ID_ATI, 0x7318, op, AMD_NAVI10}, \ + {PCI_VENDOR_ID_ATI, 0x7319, op, AMD_NAVI10}, \ + {PCI_VENDOR_ID_ATI, 0x731a, op, AMD_NAVI10}, \ + {PCI_VENDOR_ID_ATI, 0x731b, op, AMD_NAVI10}, \ + {PCI_VENDOR_ID_ATI, 0x731e, op, AMD_NAVI10}, \ + {PCI_VENDOR_ID_ATI, 0x731f, op, AMD_NAVI10} -#define AMD_NAVI14(op) \ - {PCI_VENDOR_ID_ATI, 0x7340, op}, \ - {PCI_VENDOR_ID_ATI, 0x7341, op}, \ - {PCI_VENDOR_ID_ATI, 0x7347, op}, \ - {PCI_VENDOR_ID_ATI, 0x734F, op} +#define _AMD_NAVI14(op) \ + {PCI_VENDOR_ID_ATI, 0x7340, op, AMD_NAVI14}, \ + {PCI_VENDOR_ID_ATI, 0x7341, op, AMD_NAVI14}, \ + {PCI_VENDOR_ID_ATI, 0x7347, op, AMD_NAVI14}, \ + {PCI_VENDOR_ID_ATI, 0x734F, op, AMD_NAVI14} + +#define _AMD_NAVI12(op) \ + {PCI_VENDOR_ID_ATI, 0x7360, op, AMD_NAVI12}, \ + {PCI_VENDOR_ID_ATI, 0x7362, op, AMD_NAVI12} static struct vendor_reset_cfg vendor_reset_devices[] = { - AMD_POLARIS10(&amd_polaris10_ops), - AMD_POLARIS11(&amd_polaris10_ops), - AMD_POLARIS12(&amd_polaris10_ops), - AMD_VEGA10(&amd_vega10_ops), - AMD_VEGA20(&amd_vega20_ops), - AMD_NAVI10(&amd_navi10_ops), - AMD_NAVI14(&amd_navi10_ops), + _AMD_POLARIS10(&amd_polaris10_ops), + _AMD_POLARIS11(&amd_polaris10_ops), + _AMD_POLARIS12(&amd_polaris10_ops), + _AMD_VEGA10(&amd_vega10_ops), + _AMD_VEGA20(&amd_vega20_ops), + _AMD_NAVI10(&amd_navi10_ops), + _AMD_NAVI14(&amd_navi10_ops), + _AMD_NAVI12(&amd_navi10_ops), {0}, }; diff --git a/src/hooks.c b/src/hooks.c index fb2a39e..68d13d1 100644 --- a/src/hooks.c +++ b/src/hooks.c @@ -43,6 +43,7 @@ static int hooked_pci_dev_specific_reset(struct pci_dev *dev, int probe) if (cfg->vendor) { vdev.pdev = dev; + vdev.info = cfg->info; if (cfg->ops->pre_reset && (ret = cfg->ops->pre_reset(&vdev)) && ret) return ret; diff --git a/src/vendor-reset-dev.h b/src/vendor-reset-dev.h index ad6a308..3d11b24 100644 --- a/src/vendor-reset-dev.h +++ b/src/vendor-reset-dev.h @@ -27,6 +27,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA struct vendor_reset_dev { struct pci_dev *pdev; + unsigned long info; int reset_ret; @@ -54,6 +55,9 @@ struct vendor_reset_cfg /* the reset operations */ const struct vendor_reset_ops * ops; + + /* device type for combined ops */ + unsigned long info; }; #endif diff --git a/src/vendor-reset.c b/src/vendor-reset.c index deba7e2..b4e40d5 100644 --- a/src/vendor-reset.c +++ b/src/vendor-reset.c @@ -68,6 +68,7 @@ static long vendor_reset_ioctl_reset(struct file * filp, unsigned long arg) } vdev.pdev = pcidev; + vdev.info = entry->info; /* we probably always want to lock the device */ if (!pci_cfg_access_trylock(pcidev))