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79 lines
2.1 KiB
C
79 lines
2.1 KiB
C
/*
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Vendor Reset - Vendor Specific Reset
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Copyright (C) 2020 Geoffrey McRae <geoff@hostfission.com>
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Copyright (C) 2020 Adam Madsen <adam@ajmadsen.com>
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This program is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free Software
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Foundation; either version 2 of the License, or (at your option) any later
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version.
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This program is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/delay.h>
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#include "bif/bif_4_1_d.h"
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#include "atom-types.h"
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#include "atombios.h"
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#include "common.h"
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#include "compat.h"
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#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b /* from amdgpu.h */
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/* from vi.c */
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static int vi_gpu_pci_config_reset(struct amd_fake_dev *adev)
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{
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u32 i;
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dev_info(adev->dev, "GPU pci config reset\n");
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/* reset */
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pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
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udelay(100);
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/* wait for asic to come out of reset */
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for (i = 0; i < 100000; i++)
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{
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if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff)
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{
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return 0;
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}
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udelay(1);
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}
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return -EINVAL;
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}
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static int amd_polaris10_reset(struct vendor_reset_dev *vdev)
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{
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int ret = 0;
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struct amd_vendor_private *priv = amd_private(vdev);
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struct amd_fake_dev *adev = &priv->adev;
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ret = amd_fake_dev_init(adev, vdev);
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if (ret)
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return ret;
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/* pre-firmware constant */
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adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0;
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amdgpu_atombios_scratch_regs_engine_hung(adev, true);
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ret = vi_gpu_pci_config_reset(adev);
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amdgpu_atombios_scratch_regs_engine_hung(adev, false);
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amd_fake_dev_fini(adev);
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return ret;
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}
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const struct vendor_reset_ops amd_polaris10_ops = {
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.pre_reset = amd_common_pre_reset,
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.reset = amd_polaris10_reset,
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.post_reset = amd_common_post_reset,
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}; |