run cargo fmt on repo

03_uart1/src/gpio.rs

@@ -22,8 +22,8 @@
  * SOFTWARE.
  */
 
-use volatile_register::RW;
 use super::MMIO_BASE;
+use volatile_register::RW;
 
 pub const GPFSEL1: *const RW<u32> = (MMIO_BASE + 0x0020_0004) as *const RW<u32>;
 pub const GPPUD: *const RW<u32> = (MMIO_BASE + 0x0020_0094) as *const RW<u32>;

03_uart1/src/uart.rs

@@ -23,8 +23,8 @@
  */
 
 use super::MMIO_BASE;
-use volatile_register::*;
 use gpio;
+use volatile_register::*;
 
 const MINI_UART_BASE: u32 = MMIO_BASE + 0x21_5000;
 

04_mailboxes/src/gpio.rs

@@ -22,8 +22,8 @@
  * SOFTWARE.
  */
 
-use volatile_register::RW;
 use super::MMIO_BASE;
+use volatile_register::RW;
 
 pub const GPFSEL1: *const RW<u32> = (MMIO_BASE + 0x0020_0004) as *const RW<u32>;
 pub const GPPUD: *const RW<u32> = (MMIO_BASE + 0x0020_0094) as *const RW<u32>;

04_mailboxes/src/main.rs

@@ -30,8 +30,8 @@ extern crate volatile_register;
 
 const MMIO_BASE: u32 = 0x3F00_0000;
 
-mod mbox;
 mod gpio;
+mod mbox;
 mod uart;
 
 use core::sync::atomic::{compiler_fence, Ordering};

04_mailboxes/src/uart.rs

@@ -23,8 +23,8 @@
  */
 
 use super::MMIO_BASE;
-use volatile_register::*;
 use gpio;
+use volatile_register::*;
 
 const MINI_UART_BASE: u32 = MMIO_BASE + 0x21_5000;
 

05_uart0/src/gpio.rs

@@ -22,8 +22,8 @@
  * SOFTWARE.
  */
 
-use volatile_register::RW;
 use super::MMIO_BASE;
+use volatile_register::RW;
 
 pub const GPFSEL1: *const RW<u32> = (MMIO_BASE + 0x0020_0004) as *const RW<u32>;
 pub const GPPUD: *const RW<u32> = (MMIO_BASE + 0x0020_0094) as *const RW<u32>;

05_uart0/src/main.rs

@@ -30,8 +30,8 @@ extern crate volatile_register;
 
 const MMIO_BASE: u32 = 0x3F00_0000;
 
-mod mbox;
 mod gpio;
+mod mbox;
 mod uart;
 
 use core::sync::atomic::{compiler_fence, Ordering};

05_uart0/src/uart.rs

@@ -23,10 +23,10 @@
  */
 
 use super::MMIO_BASE;
-use volatile_register::*;
-use mbox;
-use gpio;
 use core::sync::atomic::{compiler_fence, Ordering};
+use gpio;
+use mbox;
+use volatile_register::*;
 
 const UART_BASE: u32 = MMIO_BASE + 0x20_1000;
 

06_raspbootin64/src/gpio.rs

@@ -22,8 +22,8 @@
  * SOFTWARE.
  */
 
-use volatile_register::RW;
 use super::MMIO_BASE;
+use volatile_register::RW;
 
 pub const GPFSEL1: *const RW<u32> = (MMIO_BASE + 0x0020_0004) as *const RW<u32>;
 pub const GPPUD: *const RW<u32> = (MMIO_BASE + 0x0020_0094) as *const RW<u32>;