Add compiler fence before mailbox signaling

05_uart0/src/main.rs

@@ -35,6 +35,8 @@ mod mbox;
 mod gpio;
 mod uart;
 
+use core::sync::atomic::{compiler_fence, Ordering};
+
 fn main() {
     let mut mbox = mbox::Mbox::new();
     let uart = uart::Uart::new();
@@ -54,6 +56,11 @@ fn main() {
     mbox.buffer[6] = 0;
     mbox.buffer[7] = mbox::tag::LAST;
 
+    // Insert a compiler fence that ensures that all stores to the
+    // mbox buffer are finished before the GPU is signaled (which is
+    // done by a store operation as well).
+    compiler_fence(Ordering::SeqCst);
+
     // send the message to the GPU and receive answer
     let serial_avail = match mbox.call(mbox::channel::PROP) {
         Err(_) => false,

05_uart0/src/uart.rs

@@ -26,6 +26,7 @@ use super::MMIO_BASE;
 use volatile_register::*;
 use mbox;
 use gpio;
+use core::sync::atomic::{compiler_fence, Ordering};
 
 const UART_BASE: u32 = MMIO_BASE + 0x201000;
 
@@ -77,6 +78,11 @@ impl Uart {
         mbox.buffer[7] = 0; // skip turbo setting
         mbox.buffer[8] = mbox::tag::LAST;
 
+        // Insert a compiler fence that ensures that all stores to the
+        // mbox buffer are finished before the GPU is signaled (which
+        // is done by a store operation as well).
+        compiler_fence(Ordering::SeqCst);
+
         if let Err(_) = mbox.call(mbox::channel::PROP) {
             return Err(UartError::MailboxError); // Abort if UART clocks couldn't be set
         };