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@ -127,7 +127,7 @@ register_structs! {
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}
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/// The driver's mutex protected part.
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struct PL011UartInner {
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pub struct PL011UartInner {
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base_addr: usize,
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chars_written: usize,
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}
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@ -151,13 +151,30 @@ impl ops::Deref for PL011UartInner {
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}
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impl PL011UartInner {
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const fn new(base_addr: usize) -> PL011UartInner {
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pub const unsafe fn new(base_addr: usize) -> PL011UartInner {
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PL011UartInner {
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base_addr,
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chars_written: 0,
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}
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}
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/// Set up baud rate and characteristics.
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///
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/// Results in 8N1 and 115200 baud (if the clk has been previously set to 4 MHz by the
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/// firmware).
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pub fn init(&self) {
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// Turn it off temporarily.
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self.CR.set(0);
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self.ICR.write(ICR::ALL::CLEAR);
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self.IBRD.write(IBRD::IBRD.val(26)); // Results in 115200 baud for UART Clk of 48 MHz.
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self.FBRD.write(FBRD::FBRD.val(3));
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self.LCRH
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.write(LCRH::WLEN::EightBit + LCRH::FEN::FifosEnabled); // 8N1 + Fifo on
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self.CR
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.write(CR::UARTEN::Enabled + CR::TXE::Enabled + CR::RXE::Enabled);
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}
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/// Return a pointer to the register block.
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fn ptr(&self) -> *const RegisterBlock {
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self.base_addr as *const _
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@ -165,12 +182,8 @@ impl PL011UartInner {
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/// Send a character.
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fn write_char(&mut self, c: char) {
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// Wait until we can send.
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loop {
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if !self.FR.is_set(FR::TXFF) {
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break;
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}
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// Spin while TX FIFO full is set, waiting for an empty slot.
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while self.FR.matches_all(FR::TXFF::SET) {
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arch::nop();
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}
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@ -205,6 +218,11 @@ impl fmt::Write for PL011UartInner {
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}
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}
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//--------------------------------------------------------------------------------------------------
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// Export the inner struct so that BSPs can use it for the panic handler
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//--------------------------------------------------------------------------------------------------
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pub use PL011UartInner as PanicUart;
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//--------------------------------------------------------------------------------------------------
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// BSP-public
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//--------------------------------------------------------------------------------------------------
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@ -235,26 +253,9 @@ impl interface::driver::DeviceDriver for PL011Uart {
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"PL011Uart"
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}
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/// Set up baud rate and characteristics
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///
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/// Results in 8N1 and 115200 baud (if the clk has been previously set to 4 MHz by the
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/// firmware).
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fn init(&self) -> interface::driver::Result {
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let mut r = &self.inner;
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r.lock(|inner| {
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// Turn it off temporarily.
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inner.CR.set(0);
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inner.ICR.write(ICR::ALL::CLEAR);
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inner.IBRD.write(IBRD::IBRD.val(26)); // Results in 115200 baud for UART Clk of 48 MHz.
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inner.FBRD.write(FBRD::FBRD.val(3));
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inner
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.LCRH
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.write(LCRH::WLEN::EightBit + LCRH::FEN::FifosEnabled); // 8N1 + Fifo on
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inner
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.CR
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.write(CR::UARTEN::Enabled + CR::TXE::Enabled + CR::RXE::Enabled);
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});
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r.lock(|inner| inner.init());
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Ok(())
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}
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@ -277,13 +278,11 @@ impl interface::console::Write for PL011Uart {
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fn flush(&self) {
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let mut r = &self.inner;
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// Spin until the TX FIFO empty flag is set.
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r.lock(|inner| loop {
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if inner.FR.is_set(FR::TXFE) {
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break;
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// Spin until TX FIFO empty is set.
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r.lock(|inner| {
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while !inner.FR.matches_all(FR::TXFE::SET) {
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arch::nop();
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}
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arch::nop();
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});
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}
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}
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@ -292,12 +291,8 @@ impl interface::console::Read for PL011Uart {
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fn read_char(&self) -> char {
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let mut r = &self.inner;
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r.lock(|inner| {
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// Wait until buffer is filled.
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loop {
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if !inner.FR.is_set(FR::RXFE) {
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break;
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}
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// Spin while RX FIFO empty is set.
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while inner.FR.matches_all(FR::RXFE::SET) {
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arch::nop();
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}
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@ -315,12 +310,10 @@ impl interface::console::Read for PL011Uart {
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fn clear(&self) {
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let mut r = &self.inner;
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r.lock(|inner| loop {
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// Read from the RX FIFO until the empty bit is '1'.
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if !inner.FR.is_set(FR::RXFE) {
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r.lock(|inner| {
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// Read from the RX FIFO until it is indicating empty.
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while !inner.FR.matches_all(FR::RXFE::SET) {
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inner.DR.get();
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} else {
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break;
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}
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})
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}
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Andre Richter
5 years ago