Add code for tutorial 10
Andre Richter
5 years ago
parent
434ac5851d
commit
d5cd571ce5
@ -0,0 +1,10 @@
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{
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"editor.formatOnSave": true,
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"rust.features": [
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"bsp_rpi3"
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],
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"rust.all_targets": false,
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"editor.rulers": [
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100
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],
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}
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@ -0,0 +1,42 @@
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# This file is automatically @generated by Cargo.
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# It is not intended for manual editing.
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[[package]]
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name = "cortex-a"
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version = "2.7.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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"register 0.3.3 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "kernel"
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version = "0.1.0"
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dependencies = [
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"cortex-a 2.7.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"register 0.3.3 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "r0"
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version = "0.2.2"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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name = "register"
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version = "0.3.3"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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"tock-registers 0.3.0 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "tock-registers"
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version = "0.3.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[metadata]
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"checksum cortex-a 2.7.0 (registry+https://github.com/rust-lang/crates.io-index)" = "cbb16c411ab74044f174746a6cbae67bcdebea126e376b5441e5986e6a6aa950"
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"checksum r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)" = "e2a38df5b15c8d5c7e8654189744d8e396bddc18ad48041a500ce52d6948941f"
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"checksum register 0.3.3 (registry+https://github.com/rust-lang/crates.io-index)" = "469bb5ddde81d67fb8bba4e14d77689b8166cfd077abe7530591cefe29d05823"
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"checksum tock-registers 0.3.0 (registry+https://github.com/rust-lang/crates.io-index)" = "c758f5195a2e0df9d9fecf6f506506b2766ff74cf64db1e995c87e2761a5c3e2"
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@ -0,0 +1,21 @@
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[package]
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name = "kernel"
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version = "0.1.0"
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authors = ["Andre Richter <andre.o.richter@gmail.com>"]
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edition = "2018"
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[package.metadata.cargo-xbuild]
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sysroot_path = "../xbuild_sysroot"
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# The features section is used to select the target board.
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[features]
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default = []
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bsp_rpi3 = ["cortex-a", "register"]
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bsp_rpi4 = ["cortex-a", "register"]
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[dependencies]
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r0 = "0.2.*"
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# Optional dependencies
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cortex-a = { version = "2.*", optional = true }
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register = { version = "0.3.*", optional = true }
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@ -0,0 +1,127 @@
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## SPDX-License-Identifier: MIT
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##
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## Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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# Default to the RPi3
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ifndef BSP
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BSP = rpi3
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endif
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# BSP-specific arguments
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ifeq ($(BSP),rpi3)
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TARGET = aarch64-unknown-none-softfloat
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OUTPUT = kernel8.img
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QEMU_BINARY = qemu-system-aarch64
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QEMU_MACHINE_TYPE = raspi3
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QEMU_MISC_ARGS = -serial stdio
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OPENOCD_ARG = -f /openocd/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg -f /openocd/rpi3.cfg
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JTAG_BOOT_IMAGE = jtag_boot_rpi3.img
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LINKER_FILE = src/bsp/rpi/link.ld
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RUSTC_MISC_ARGS = -C target-cpu=cortex-a53
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else ifeq ($(BSP),rpi4)
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TARGET = aarch64-unknown-none-softfloat
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OUTPUT = kernel8.img
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# QEMU_BINARY = qemu-system-aarch64
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# QEMU_MACHINE_TYPE =
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# QEMU_MISC_ARGS = -serial stdio
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OPENOCD_ARG = -f /openocd/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg -f /openocd/rpi4.cfg
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JTAG_BOOT_IMAGE = jtag_boot_rpi4.img
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LINKER_FILE = src/bsp/rpi/link.ld
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RUSTC_MISC_ARGS = -C target-cpu=cortex-a72
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endif
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SOURCES = $(wildcard **/*.rs) $(wildcard **/*.S) $(wildcard **/*.ld)
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XRUSTC_CMD = cargo xrustc \
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--target=$(TARGET) \
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--features bsp_$(BSP) \
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--release \
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-- \
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-C link-arg=-T$(LINKER_FILE) \
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$(RUSTC_MISC_ARGS)
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CARGO_OUTPUT = target/$(TARGET)/release/kernel
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OBJCOPY_CMD = cargo objcopy \
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-- \
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--strip-all \
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-O binary
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CONTAINER_UTILS = rustembedded/osdev-utils
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DOCKER_CMD = docker run -it --rm
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DOCKER_ARG_CURDIR = -v $(shell pwd):/work -w /work
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DOCKER_ARG_TTY = --privileged -v /dev:/dev
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DOCKER_ARG_JTAG = -v $(shell pwd)/../X1_JTAG_boot:/jtag
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DOCKER_ARG_NET = --network host
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DOCKER_EXEC_QEMU = $(QEMU_BINARY) -M $(QEMU_MACHINE_TYPE) -kernel $(OUTPUT)
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DOCKER_EXEC_RASPBOOT = raspbootcom
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DOCKER_EXEC_RASPBOOT_DEV = /dev/ttyUSB0
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# DOCKER_EXEC_RASPBOOT_DEV = /dev/ttyACM0
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.PHONY: all doc qemu chainboot clippy clean readelf objdump nm
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all: clean $(OUTPUT)
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$(CARGO_OUTPUT): $(SOURCES)
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RUSTFLAGS="-D warnings -D missing_docs" $(XRUSTC_CMD)
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$(OUTPUT): $(CARGO_OUTPUT)
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cp $< .
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$(OBJCOPY_CMD) $< $(OUTPUT)
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doc:
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cargo xdoc --target=$(TARGET) --features bsp_$(BSP) --document-private-items
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xdg-open target/$(TARGET)/doc/kernel/index.html
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ifeq ($(QEMU_MACHINE_TYPE),)
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qemu:
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@echo "This board is not yet supported for QEMU."
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else
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qemu: all
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$(DOCKER_CMD) $(DOCKER_ARG_CURDIR) $(CONTAINER_UTILS) \
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$(DOCKER_EXEC_QEMU) $(QEMU_MISC_ARGS)
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endif
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chainboot: all
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$(DOCKER_CMD) $(DOCKER_ARG_CURDIR) $(DOCKER_ARG_TTY) \
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$(CONTAINER_UTILS) $(DOCKER_EXEC_RASPBOOT) $(DOCKER_EXEC_RASPBOOT_DEV) \
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$(OUTPUT)
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jtagboot:
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$(DOCKER_CMD) $(DOCKER_ARG_TTY) $(DOCKER_ARG_JTAG) $(CONTAINER_UTILS) \
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$(DOCKER_EXEC_RASPBOOT) $(DOCKER_EXEC_RASPBOOT_DEV) \
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/jtag/$(JTAG_BOOT_IMAGE)
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openocd:
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$(DOCKER_CMD) $(DOCKER_ARG_TTY) $(DOCKER_ARG_NET) $(CONTAINER_UTILS) \
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openocd $(OPENOCD_ARG)
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define gen_gdb
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RUSTFLAGS="-D warnings -D missing_docs" $(XRUSTC_CMD) $1
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cp $(CARGO_OUTPUT) kernel_for_jtag
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$(DOCKER_CMD) $(DOCKER_ARG_CURDIR) $(DOCKER_ARG_NET) $(CONTAINER_UTILS) \
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gdb-multiarch -q kernel_for_jtag
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endef
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gdb: clean $(SOURCES)
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$(call gen_gdb,-C debuginfo=2)
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gdb-opt0: clean $(SOURCES)
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$(call gen_gdb,-C debuginfo=2 -C opt-level=0)
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clippy:
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cargo xclippy --target=$(TARGET) --features bsp_$(BSP)
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clean:
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cargo clean
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readelf:
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readelf -a kernel
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objdump:
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cargo objdump --target $(TARGET) -- -disassemble -print-imm-hex kernel
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nm:
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cargo nm --target $(TARGET) -- kernel | sort
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Binary file not shown.
Binary file not shown.
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// SPDX-License-Identifier: MIT
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//
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// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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//! Conditional exporting of processor architecture code.
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#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))]
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mod aarch64;
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#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))]
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pub use aarch64::*;
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@ -0,0 +1,133 @@
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// SPDX-License-Identifier: MIT
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//
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// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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//! AArch64.
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mod exception;
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pub mod sync;
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mod time;
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use crate::{bsp, interface};
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use cortex_a::{asm, regs::*};
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/// The entry of the `kernel` binary.
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///
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/// The function must be named `_start`, because the linker is looking for this exact name.
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///
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/// # Safety
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///
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/// - Linker script must ensure to place this function at `0x80_000`.
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#[no_mangle]
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pub unsafe extern "C" fn _start() -> ! {
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const CORE_MASK: u64 = 0x3;
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// Expect the boot core to start in EL2.
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if (bsp::BOOT_CORE_ID == MPIDR_EL1.get() & CORE_MASK)
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&& (CurrentEL.get() == CurrentEL::EL::EL2.value)
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{
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el2_to_el1_transition()
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} else {
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// If not core0, infinitely wait for events.
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wait_forever()
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}
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}
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/// Transition from EL2 to EL1.
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#[inline(always)]
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fn el2_to_el1_transition() -> ! {
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// Enable timer counter registers for EL1.
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CNTHCTL_EL2.write(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET);
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// No offset for reading the counters.
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CNTVOFF_EL2.set(0);
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// Set EL1 execution state to AArch64.
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HCR_EL2.write(HCR_EL2::RW::EL1IsAarch64);
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// Set up a simulated exception return.
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//
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// First, fake a saved program status, where all interrupts were masked and SP_EL1 was used as a
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// stack pointer.
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SPSR_EL2.write(
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SPSR_EL2::D::Masked
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+ SPSR_EL2::A::Masked
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+ SPSR_EL2::I::Masked
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+ SPSR_EL2::F::Masked
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+ SPSR_EL2::M::EL1h,
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);
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// Second, let the link register point to init().
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ELR_EL2.set(crate::runtime_init::init as *const () as u64);
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// Set up SP_EL1 (stack pointer), which will be used by EL1 once we "return" to it.
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SP_EL1.set(bsp::BOOT_CORE_STACK_START);
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// Use `eret` to "return" to EL1. This will result in execution of `reset()` in EL1.
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asm::eret()
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}
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//--------------------------------------------------------------------------------------------------
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// Global instances
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//--------------------------------------------------------------------------------------------------
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static TIMER: time::Timer = time::Timer;
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//--------------------------------------------------------------------------------------------------
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// Implementation of the kernel's architecture abstraction code
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//--------------------------------------------------------------------------------------------------
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pub use asm::nop;
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/// Spin for `n` cycles.
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pub fn spin_for_cycles(n: usize) {
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for _ in 0..n {
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asm::nop();
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}
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}
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/// Return a reference to a `interface::time::TimeKeeper` implementation.
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pub fn timer() -> &'static impl interface::time::Timer {
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&TIMER
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}
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/// Pause execution on the calling CPU core.
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#[inline(always)]
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pub fn wait_forever() -> ! {
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loop {
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asm::wfe()
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}
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}
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/// Information about the HW state.
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pub mod state {
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use cortex_a::regs::*;
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/// The current privilege level.
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pub fn current_privilege_level() -> &'static str {
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let el = CurrentEL.read_as_enum(CurrentEL::EL);
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match el {
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Some(CurrentEL::EL::Value::EL2) => "EL2",
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Some(CurrentEL::EL::Value::EL1) => "EL1",
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_ => "Unknown",
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}
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}
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#[rustfmt::skip]
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pub fn print_exception_state() {
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use super::{
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exception,
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exception::{Debug, SError, FIQ, IRQ},
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};
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use crate::println;
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let to_mask_str = |x: bool| -> &'static str {
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if x { "Masked" } else { "Unmasked" }
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};
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println!(" Debug: {}", to_mask_str(exception::is_masked::<Debug>()));
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println!(" SError: {}", to_mask_str(exception::is_masked::<SError>()));
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println!(" IRQ: {}", to_mask_str(exception::is_masked::<IRQ>()));
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println!(" FIQ: {}", to_mask_str(exception::is_masked::<FIQ>()));
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}
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}
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@ -0,0 +1,44 @@
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// SPDX-License-Identifier: MIT
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//
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// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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//! Exception handling.
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use cortex_a::regs::*;
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pub trait DaifField {
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fn daif_field() -> register::Field<u32, DAIF::Register>;
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}
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pub struct Debug;
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pub struct SError;
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pub struct IRQ;
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pub struct FIQ;
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impl DaifField for Debug {
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fn daif_field() -> register::Field<u32, DAIF::Register> {
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DAIF::D
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}
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}
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impl DaifField for SError {
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fn daif_field() -> register::Field<u32, DAIF::Register> {
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DAIF::A
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}
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}
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impl DaifField for IRQ {
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fn daif_field() -> register::Field<u32, DAIF::Register> {
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DAIF::I
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}
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}
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impl DaifField for FIQ {
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fn daif_field() -> register::Field<u32, DAIF::Register> {
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DAIF::F
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}
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}
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pub fn is_masked<T: DaifField>() -> bool {
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DAIF.is_set(T::daif_field())
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}
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// SPDX-License-Identifier: MIT
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//
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// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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//! Synchronization primitives.
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use crate::interface;
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use core::cell::UnsafeCell;
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/// A pseudo-lock for teaching purposes.
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///
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/// Used to introduce [interior mutability].
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///
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/// In contrast to a real Mutex implementation, does not protect against concurrent access to the
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/// contained data. This part is preserved for later lessons.
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///
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/// The lock will only be used as long as it is safe to do so, i.e. as long as the kernel is
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/// executing single-threaded, aka only running on a single core with interrupts disabled.
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///
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/// [interior mutability]: https://doc.rust-lang.org/std/cell/index.html
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pub struct NullLock<T: ?Sized> {
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data: UnsafeCell<T>,
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}
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unsafe impl<T: ?Sized + Send> Send for NullLock<T> {}
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unsafe impl<T: ?Sized + Send> Sync for NullLock<T> {}
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impl<T> NullLock<T> {
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pub const fn new(data: T) -> NullLock<T> {
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NullLock {
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data: UnsafeCell::new(data),
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}
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}
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}
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impl<T> interface::sync::Mutex for &NullLock<T> {
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type Data = T;
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fn lock<R>(&mut self, f: impl FnOnce(&mut Self::Data) -> R) -> R {
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// In a real lock, there would be code encapsulating this line that ensures that this
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// mutable reference will ever only be given out once at a time.
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f(unsafe { &mut *self.data.get() })
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}
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}
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@ -0,0 +1,77 @@
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// SPDX-License-Identifier: MIT
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//
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// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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//! Timer primitives.
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use crate::{interface, warn};
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use core::time::Duration;
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use cortex_a::regs::*;
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const NS_PER_S: u64 = 1_000_000_000;
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pub struct Timer;
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impl interface::time::Timer for Timer {
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fn resolution(&self) -> Duration {
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Duration::from_nanos(NS_PER_S / (CNTFRQ_EL0.get() as u64))
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}
|
||||
|
||||
fn uptime(&self) -> Duration {
|
||||
let frq: u64 = CNTFRQ_EL0.get() as u64;
|
||||
let current_count: u64 = CNTPCT_EL0.get() * NS_PER_S;
|
||||
|
||||
Duration::from_nanos(current_count / frq)
|
||||
}
|
||||
|
||||
fn spin_for(&self, duration: Duration) {
|
||||
// Instantly return on zero.
|
||||
if duration.as_nanos() == 0 {
|
||||
return;
|
||||
}
|
||||
|
||||
// Calculate the register compare value.
|
||||
let frq = CNTFRQ_EL0.get() as u64;
|
||||
let x = match frq.checked_mul(duration.as_nanos() as u64) {
|
||||
None => {
|
||||
warn!("Spin duration too long, skipping");
|
||||
return;
|
||||
}
|
||||
Some(val) => val,
|
||||
};
|
||||
let tval = x / NS_PER_S;
|
||||
|
||||
// Check if it is within supported bounds.
|
||||
let warn: Option<&str> = if tval == 0 {
|
||||
Some("smaller")
|
||||
} else if tval > u32::max_value().into() {
|
||||
Some("bigger")
|
||||
} else {
|
||||
None
|
||||
};
|
||||
|
||||
if let Some(w) = warn {
|
||||
warn!(
|
||||
"Spin duration {} than architecturally supported, skipping",
|
||||
w
|
||||
);
|
||||
return;
|
||||
}
|
||||
|
||||
// Set the compare value register.
|
||||
CNTP_TVAL_EL0.set(tval as u32);
|
||||
|
||||
// Kick off the counting. // Disable timer interrupt.
|
||||
CNTP_CTL_EL0.modify(CNTP_CTL_EL0::ENABLE::SET + CNTP_CTL_EL0::IMASK::SET);
|
||||
|
||||
loop {
|
||||
// ISTATUS will be '1' when cval ticks have passed. Busy-check it.
|
||||
if CNTP_CTL_EL0.is_set(CNTP_CTL_EL0::ISTATUS) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// Disable counting again.
|
||||
CNTP_CTL_EL0.modify(CNTP_CTL_EL0::ENABLE::CLEAR);
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,13 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! Conditional exporting of Board Support Packages.
|
||||
|
||||
mod driver;
|
||||
|
||||
#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))]
|
||||
mod rpi;
|
||||
|
||||
#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))]
|
||||
pub use rpi::*;
|
||||
@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! Drivers.
|
||||
|
||||
#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))]
|
||||
mod bcm;
|
||||
|
||||
#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))]
|
||||
pub use bcm::*;
|
||||
@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! BCM driver top level.
|
||||
|
||||
mod bcm2xxx_gpio;
|
||||
mod bcm2xxx_pl011_uart;
|
||||
|
||||
pub use bcm2xxx_gpio::GPIO;
|
||||
pub use bcm2xxx_pl011_uart::PL011Uart;
|
||||
@ -0,0 +1,157 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! GPIO driver.
|
||||
|
||||
use crate::{arch, arch::sync::NullLock, interface};
|
||||
use core::ops;
|
||||
use register::{mmio::ReadWrite, register_bitfields};
|
||||
|
||||
// GPIO registers.
|
||||
//
|
||||
// Descriptions taken from
|
||||
// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
|
||||
register_bitfields! {
|
||||
u32,
|
||||
|
||||
/// GPIO Function Select 1
|
||||
GPFSEL1 [
|
||||
/// Pin 15
|
||||
FSEL15 OFFSET(15) NUMBITS(3) [
|
||||
Input = 0b000,
|
||||
Output = 0b001,
|
||||
AltFunc0 = 0b100 // PL011 UART RX
|
||||
|
||||
],
|
||||
|
||||
/// Pin 14
|
||||
FSEL14 OFFSET(12) NUMBITS(3) [
|
||||
Input = 0b000,
|
||||
Output = 0b001,
|
||||
AltFunc0 = 0b100 // PL011 UART TX
|
||||
]
|
||||
],
|
||||
|
||||
/// GPIO Pull-up/down Clock Register 0
|
||||
GPPUDCLK0 [
|
||||
/// Pin 15
|
||||
PUDCLK15 OFFSET(15) NUMBITS(1) [
|
||||
NoEffect = 0,
|
||||
AssertClock = 1
|
||||
],
|
||||
|
||||
/// Pin 14
|
||||
PUDCLK14 OFFSET(14) NUMBITS(1) [
|
||||
NoEffect = 0,
|
||||
AssertClock = 1
|
||||
]
|
||||
]
|
||||
}
|
||||
|
||||
#[allow(non_snake_case)]
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
pub GPFSEL0: ReadWrite<u32>, // 0x00
|
||||
pub GPFSEL1: ReadWrite<u32, GPFSEL1::Register>, // 0x04
|
||||
pub GPFSEL2: ReadWrite<u32>, // 0x08
|
||||
pub GPFSEL3: ReadWrite<u32>, // 0x0C
|
||||
pub GPFSEL4: ReadWrite<u32>, // 0x10
|
||||
pub GPFSEL5: ReadWrite<u32>, // 0x14
|
||||
__reserved_0: u32, // 0x18
|
||||
GPSET0: ReadWrite<u32>, // 0x1C
|
||||
GPSET1: ReadWrite<u32>, // 0x20
|
||||
__reserved_1: u32, //
|
||||
GPCLR0: ReadWrite<u32>, // 0x28
|
||||
__reserved_2: [u32; 2], //
|
||||
GPLEV0: ReadWrite<u32>, // 0x34
|
||||
GPLEV1: ReadWrite<u32>, // 0x38
|
||||
__reserved_3: u32, //
|
||||
GPEDS0: ReadWrite<u32>, // 0x40
|
||||
GPEDS1: ReadWrite<u32>, // 0x44
|
||||
__reserved_4: [u32; 7], //
|
||||
GPHEN0: ReadWrite<u32>, // 0x64
|
||||
GPHEN1: ReadWrite<u32>, // 0x68
|
||||
__reserved_5: [u32; 10], //
|
||||
pub GPPUD: ReadWrite<u32>, // 0x94
|
||||
pub GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>, // 0x98
|
||||
pub GPPUDCLK1: ReadWrite<u32>, // 0x9C
|
||||
}
|
||||
|
||||
/// The driver's private data.
|
||||
struct GPIOInner {
|
||||
base_addr: usize,
|
||||
}
|
||||
|
||||
/// Deref to RegisterBlock.
|
||||
impl ops::Deref for GPIOInner {
|
||||
type Target = RegisterBlock;
|
||||
|
||||
fn deref(&self) -> &Self::Target {
|
||||
unsafe { &*self.ptr() }
|
||||
}
|
||||
}
|
||||
|
||||
impl GPIOInner {
|
||||
const fn new(base_addr: usize) -> GPIOInner {
|
||||
GPIOInner { base_addr }
|
||||
}
|
||||
|
||||
/// Return a pointer to the register block.
|
||||
fn ptr(&self) -> *const RegisterBlock {
|
||||
self.base_addr as *const _
|
||||
}
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// BSP-public
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
use interface::sync::Mutex;
|
||||
|
||||
/// The driver's main struct.
|
||||
pub struct GPIO {
|
||||
inner: NullLock<GPIOInner>,
|
||||
}
|
||||
|
||||
impl GPIO {
|
||||
pub const unsafe fn new(base_addr: usize) -> GPIO {
|
||||
GPIO {
|
||||
inner: NullLock::new(GPIOInner::new(base_addr)),
|
||||
}
|
||||
}
|
||||
|
||||
/// Map PL011 UART as standard output.
|
||||
///
|
||||
/// TX to pin 14
|
||||
/// RX to pin 15
|
||||
pub fn map_pl011_uart(&self) {
|
||||
let mut r = &self.inner;
|
||||
r.lock(|inner| {
|
||||
// Map to pins.
|
||||
inner
|
||||
.GPFSEL1
|
||||
.modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0);
|
||||
|
||||
// Enable pins 14 and 15.
|
||||
inner.GPPUD.set(0);
|
||||
arch::spin_for_cycles(150);
|
||||
|
||||
inner
|
||||
.GPPUDCLK0
|
||||
.write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
|
||||
arch::spin_for_cycles(150);
|
||||
|
||||
inner.GPPUDCLK0.set(0);
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// OS interface implementations
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
|
||||
impl interface::driver::DeviceDriver for GPIO {
|
||||
fn compatible(&self) -> &str {
|
||||
"GPIO"
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,332 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! PL011 UART driver.
|
||||
|
||||
use crate::{arch, arch::sync::NullLock, interface};
|
||||
use core::{fmt, ops};
|
||||
use register::{mmio::*, register_bitfields};
|
||||
|
||||
// PL011 UART registers.
|
||||
//
|
||||
// Descriptions taken from
|
||||
// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
|
||||
register_bitfields! {
|
||||
u32,
|
||||
|
||||
/// Flag Register
|
||||
FR [
|
||||
/// Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
|
||||
/// Line Control Register, UARTLCR_ LCRH.
|
||||
///
|
||||
/// If the FIFO is disabled, this bit is set when the transmit holding register is empty. If
|
||||
/// the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does
|
||||
/// not indicate if there is data in the transmit shift register.
|
||||
TXFE OFFSET(7) NUMBITS(1) [],
|
||||
|
||||
/// Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the
|
||||
/// UARTLCR_ LCRH Register.
|
||||
///
|
||||
/// If the FIFO is disabled, this bit is set when the transmit holding register is full. If
|
||||
/// the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
|
||||
TXFF OFFSET(5) NUMBITS(1) [],
|
||||
|
||||
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
|
||||
/// UARTLCR_H Register.
|
||||
///
|
||||
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
|
||||
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
|
||||
RXFE OFFSET(4) NUMBITS(1) []
|
||||
],
|
||||
|
||||
/// Integer Baud rate divisor
|
||||
IBRD [
|
||||
/// Integer Baud rate divisor
|
||||
IBRD OFFSET(0) NUMBITS(16) []
|
||||
],
|
||||
|
||||
/// Fractional Baud rate divisor
|
||||
FBRD [
|
||||
/// Fractional Baud rate divisor
|
||||
FBRD OFFSET(0) NUMBITS(6) []
|
||||
],
|
||||
|
||||
/// Line Control register
|
||||
LCRH [
|
||||
/// Word length. These bits indicate the number of data bits transmitted or received in a
|
||||
/// frame.
|
||||
WLEN OFFSET(5) NUMBITS(2) [
|
||||
FiveBit = 0b00,
|
||||
SixBit = 0b01,
|
||||
SevenBit = 0b10,
|
||||
EightBit = 0b11
|
||||
],
|
||||
|
||||
/// Enable FIFOs:
|
||||
///
|
||||
/// 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding
|
||||
/// registers
|
||||
///
|
||||
/// 1 = transmit and receive FIFO buffers are enabled (FIFO mode).
|
||||
FEN OFFSET(4) NUMBITS(1) [
|
||||
FifosDisabled = 0,
|
||||
FifosEnabled = 1
|
||||
]
|
||||
],
|
||||
|
||||
/// Control Register
|
||||
CR [
|
||||
/// Receive enable. If this bit is set to 1, the receive section of the UART is enabled.
|
||||
/// Data reception occurs for UART signals. When the UART is disabled in the middle of
|
||||
/// reception, it completes the current character before stopping.
|
||||
RXE OFFSET(9) NUMBITS(1) [
|
||||
Disabled = 0,
|
||||
Enabled = 1
|
||||
],
|
||||
|
||||
/// Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled.
|
||||
/// Data transmission occurs for UART signals. When the UART is disabled in the middle of
|
||||
/// transmission, it completes the current character before stopping.
|
||||
TXE OFFSET(8) NUMBITS(1) [
|
||||
Disabled = 0,
|
||||
Enabled = 1
|
||||
],
|
||||
|
||||
/// UART enable
|
||||
UARTEN OFFSET(0) NUMBITS(1) [
|
||||
/// If the UART is disabled in the middle of transmission or reception, it completes the
|
||||
/// current character before stopping.
|
||||
Disabled = 0,
|
||||
Enabled = 1
|
||||
]
|
||||
],
|
||||
|
||||
/// Interrupt Clear Register
|
||||
ICR [
|
||||
/// Meta field for all pending interrupts
|
||||
ALL OFFSET(0) NUMBITS(11) []
|
||||
]
|
||||
}
|
||||
|
||||
#[allow(non_snake_case)]
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
DR: ReadWrite<u32>, // 0x00
|
||||
__reserved_0: [u32; 5], // 0x04
|
||||
FR: ReadOnly<u32, FR::Register>, // 0x18
|
||||
__reserved_1: [u32; 2], // 0x1c
|
||||
IBRD: WriteOnly<u32, IBRD::Register>, // 0x24
|
||||
FBRD: WriteOnly<u32, FBRD::Register>, // 0x28
|
||||
LCRH: WriteOnly<u32, LCRH::Register>, // 0x2C
|
||||
CR: WriteOnly<u32, CR::Register>, // 0x30
|
||||
__reserved_2: [u32; 4], // 0x34
|
||||
ICR: WriteOnly<u32, ICR::Register>, // 0x44
|
||||
}
|
||||
|
||||
/// The driver's mutex protected part.
|
||||
struct PL011UartInner {
|
||||
base_addr: usize,
|
||||
chars_written: usize,
|
||||
}
|
||||
|
||||
/// Deref to RegisterBlock.
|
||||
///
|
||||
/// Allows writing
|
||||
/// ```
|
||||
/// self.DR.read()
|
||||
/// ```
|
||||
/// instead of something along the lines of
|
||||
/// ```
|
||||
/// unsafe { (*PL011UartInner::ptr()).DR.read() }
|
||||
/// ```
|
||||
impl ops::Deref for PL011UartInner {
|
||||
type Target = RegisterBlock;
|
||||
|
||||
fn deref(&self) -> &Self::Target {
|
||||
unsafe { &*self.ptr() }
|
||||
}
|
||||
}
|
||||
|
||||
impl PL011UartInner {
|
||||
const fn new(base_addr: usize) -> PL011UartInner {
|
||||
PL011UartInner {
|
||||
base_addr,
|
||||
chars_written: 0,
|
||||
}
|
||||
}
|
||||
|
||||
/// Return a pointer to the register block.
|
||||
fn ptr(&self) -> *const RegisterBlock {
|
||||
self.base_addr as *const _
|
||||
}
|
||||
|
||||
/// Send a character.
|
||||
fn write_char(&mut self, c: char) {
|
||||
// Wait until we can send.
|
||||
loop {
|
||||
if !self.FR.is_set(FR::TXFF) {
|
||||
break;
|
||||
}
|
||||
|
||||
arch::nop();
|
||||
}
|
||||
|
||||
// Write the character to the buffer.
|
||||
self.DR.set(c as u32);
|
||||
}
|
||||
}
|
||||
|
||||
/// Implementing `core::fmt::Write` enables usage of the `format_args!` macros, which in turn are
|
||||
/// used to implement the `kernel`'s `print!` and `println!` macros. By implementing `write_str()`,
|
||||
/// we get `write_fmt()` automatically.
|
||||
///
|
||||
/// The function takes an `&mut self`, so it must be implemented for the inner struct.
|
||||
///
|
||||
/// See [`src/print.rs`].
|
||||
///
|
||||
/// [`src/print.rs`]: ../../print/index.html
|
||||
impl fmt::Write for PL011UartInner {
|
||||
fn write_str(&mut self, s: &str) -> fmt::Result {
|
||||
for c in s.chars() {
|
||||
// Convert newline to carrige return + newline.
|
||||
if c == '\n' {
|
||||
self.write_char('\r')
|
||||
}
|
||||
|
||||
self.write_char(c);
|
||||
}
|
||||
|
||||
self.chars_written += s.len();
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// BSP-public
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
|
||||
/// The driver's main struct.
|
||||
pub struct PL011Uart {
|
||||
inner: NullLock<PL011UartInner>,
|
||||
}
|
||||
|
||||
impl PL011Uart {
|
||||
/// # Safety
|
||||
///
|
||||
/// The user must ensure to provide the correct `base_addr`.
|
||||
pub const unsafe fn new(base_addr: usize) -> PL011Uart {
|
||||
PL011Uart {
|
||||
inner: NullLock::new(PL011UartInner::new(base_addr)),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// OS interface implementations
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
use interface::sync::Mutex;
|
||||
|
||||
impl interface::driver::DeviceDriver for PL011Uart {
|
||||
fn compatible(&self) -> &str {
|
||||
"PL011Uart"
|
||||
}
|
||||
|
||||
/// Set up baud rate and characteristics
|
||||
///
|
||||
/// Results in 8N1 and 115200 baud (if the clk has been previously set to 4 MHz by the
|
||||
/// firmware).
|
||||
fn init(&self) -> interface::driver::Result {
|
||||
let mut r = &self.inner;
|
||||
r.lock(|inner| {
|
||||
// Turn it off temporarily.
|
||||
inner.CR.set(0);
|
||||
|
||||
inner.ICR.write(ICR::ALL::CLEAR);
|
||||
inner.IBRD.write(IBRD::IBRD.val(26)); // Results in 115200 baud for UART Clk of 48 MHz.
|
||||
inner.FBRD.write(FBRD::FBRD.val(3));
|
||||
inner
|
||||
.LCRH
|
||||
.write(LCRH::WLEN::EightBit + LCRH::FEN::FifosEnabled); // 8N1 + Fifo on
|
||||
inner
|
||||
.CR
|
||||
.write(CR::UARTEN::Enabled + CR::TXE::Enabled + CR::RXE::Enabled);
|
||||
});
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
impl interface::console::Write for PL011Uart {
|
||||
/// Passthrough of `args` to the `core::fmt::Write` implementation, but guarded by a Mutex to
|
||||
/// serialize access.
|
||||
fn write_char(&self, c: char) {
|
||||
let mut r = &self.inner;
|
||||
r.lock(|inner| inner.write_char(c));
|
||||
}
|
||||
|
||||
fn write_fmt(&self, args: core::fmt::Arguments) -> fmt::Result {
|
||||
// Fully qualified syntax for the call to `core::fmt::Write::write:fmt()` to increase
|
||||
// readability.
|
||||
let mut r = &self.inner;
|
||||
r.lock(|inner| fmt::Write::write_fmt(inner, args))
|
||||
}
|
||||
|
||||
fn flush(&self) {
|
||||
let mut r = &self.inner;
|
||||
// Spin until the TX FIFO empty flag is set.
|
||||
r.lock(|inner| loop {
|
||||
if inner.FR.is_set(FR::TXFE) {
|
||||
break;
|
||||
}
|
||||
|
||||
arch::nop();
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
impl interface::console::Read for PL011Uart {
|
||||
fn read_char(&self) -> char {
|
||||
let mut r = &self.inner;
|
||||
r.lock(|inner| {
|
||||
// Wait until buffer is filled.
|
||||
loop {
|
||||
if !inner.FR.is_set(FR::RXFE) {
|
||||
break;
|
||||
}
|
||||
|
||||
arch::nop();
|
||||
}
|
||||
|
||||
// Read one character.
|
||||
let mut ret = inner.DR.get() as u8 as char;
|
||||
|
||||
// Convert carrige return to newline.
|
||||
if ret == '\r' {
|
||||
ret = '\n'
|
||||
}
|
||||
|
||||
ret
|
||||
})
|
||||
}
|
||||
|
||||
fn clear(&self) {
|
||||
let mut r = &self.inner;
|
||||
r.lock(|inner| loop {
|
||||
// Read from the RX FIFO until the empty bit is '1'.
|
||||
if !inner.FR.is_set(FR::RXFE) {
|
||||
inner.DR.get();
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
impl interface::console::Statistics for PL011Uart {
|
||||
fn chars_written(&self) -> usize {
|
||||
let mut r = &self.inner;
|
||||
r.lock(|inner| inner.chars_written)
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,58 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! Board Support Package for the Raspberry Pi.
|
||||
|
||||
mod memory_map;
|
||||
|
||||
use super::driver;
|
||||
use crate::interface;
|
||||
|
||||
pub const BOOT_CORE_ID: u64 = 0;
|
||||
pub const BOOT_CORE_STACK_START: u64 = 0x80_000;
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Global BSP driver instances
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
|
||||
static GPIO: driver::GPIO = unsafe { driver::GPIO::new(memory_map::mmio::GPIO_BASE) };
|
||||
static PL011_UART: driver::PL011Uart =
|
||||
unsafe { driver::PL011Uart::new(memory_map::mmio::PL011_UART_BASE) };
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Implementation of the kernel's BSP calls
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
|
||||
/// Board identification.
|
||||
pub fn board_name() -> &'static str {
|
||||
#[cfg(feature = "bsp_rpi3")]
|
||||
{
|
||||
"Raspberry Pi 3"
|
||||
}
|
||||
|
||||
#[cfg(feature = "bsp_rpi4")]
|
||||
{
|
||||
"Raspberry Pi 4"
|
||||
}
|
||||
}
|
||||
|
||||
/// Return a reference to a `console::All` implementation.
|
||||
pub fn console() -> &'static impl interface::console::All {
|
||||
&PL011_UART
|
||||
}
|
||||
|
||||
/// Return an array of references to all `DeviceDriver` compatible `BSP` drivers.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// The order of devices is the order in which `DeviceDriver::init()` is called.
|
||||
pub fn device_drivers() -> [&'static dyn interface::driver::DeviceDriver; 2] {
|
||||
[&GPIO, &PL011_UART]
|
||||
}
|
||||
|
||||
/// BSP initialization code that runs after driver init.
|
||||
pub fn post_driver_init() {
|
||||
// Configure PL011Uart's output pins.
|
||||
GPIO.map_pl011_uart();
|
||||
}
|
||||
@ -0,0 +1,35 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
*/
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Set current address to the value from which the RPi starts execution */
|
||||
. = 0x80000;
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text._start) *(.text*)
|
||||
}
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata*)
|
||||
}
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data*)
|
||||
}
|
||||
|
||||
/* Align to 8 byte boundary */
|
||||
.bss ALIGN(8):
|
||||
{
|
||||
__bss_start = .;
|
||||
*(.bss*);
|
||||
__bss_end = .;
|
||||
}
|
||||
|
||||
/DISCARD/ : { *(.comment*) }
|
||||
}
|
||||
@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! The board's memory map.
|
||||
|
||||
/// Physical devices.
|
||||
#[rustfmt::skip]
|
||||
pub mod mmio {
|
||||
#[cfg(feature = "bsp_rpi3")]
|
||||
pub const BASE: usize = 0x3F00_0000;
|
||||
|
||||
#[cfg(feature = "bsp_rpi4")]
|
||||
pub const BASE: usize = 0xFE00_0000;
|
||||
|
||||
pub const GPIO_BASE: usize = BASE + 0x0020_0000;
|
||||
pub const PL011_UART_BASE: usize = BASE + 0x0020_1000;
|
||||
}
|
||||
@ -0,0 +1,129 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! Trait definitions for coupling `kernel` and `BSP` code.
|
||||
//!
|
||||
//! ```
|
||||
//! +-------------------+
|
||||
//! | Interface (Trait) |
|
||||
//! | |
|
||||
//! +--+-------------+--+
|
||||
//! ^ ^
|
||||
//! | |
|
||||
//! | |
|
||||
//! +----------+--+ +--+----------+
|
||||
//! | Kernel code | | BSP Code |
|
||||
//! | | | |
|
||||
//! +-------------+ +-------------+
|
||||
//! ```
|
||||
|
||||
/// System console operations.
|
||||
pub mod console {
|
||||
use core::fmt;
|
||||
|
||||
/// Console write functions.
|
||||
pub trait Write {
|
||||
fn write_char(&self, c: char);
|
||||
fn write_fmt(&self, args: fmt::Arguments) -> fmt::Result;
|
||||
|
||||
/// Block execution until the last character has been physically put on the TX wire
|
||||
/// (draining TX buffers/FIFOs, if any).
|
||||
fn flush(&self);
|
||||
}
|
||||
|
||||
/// Console read functions.
|
||||
pub trait Read {
|
||||
fn read_char(&self) -> char {
|
||||
' '
|
||||
}
|
||||
|
||||
/// Clear RX buffers, if any.
|
||||
fn clear(&self);
|
||||
}
|
||||
|
||||
/// Console statistics.
|
||||
pub trait Statistics {
|
||||
/// Return the number of characters written.
|
||||
fn chars_written(&self) -> usize {
|
||||
0
|
||||
}
|
||||
|
||||
/// Return the number of characters read.
|
||||
fn chars_read(&self) -> usize {
|
||||
0
|
||||
}
|
||||
}
|
||||
|
||||
/// Trait alias for a full-fledged console.
|
||||
pub trait All = Write + Read + Statistics;
|
||||
}
|
||||
|
||||
/// Synchronization primitives.
|
||||
pub mod sync {
|
||||
/// Any object implementing this trait guarantees exclusive access to the data contained within
|
||||
/// the mutex for the duration of the lock.
|
||||
///
|
||||
/// The trait follows the [Rust embedded WG's
|
||||
/// proposal](https://github.com/korken89/wg/blob/master/rfcs/0377-mutex-trait.md) and therefore
|
||||
/// provides some goodness such as [deadlock
|
||||
/// prevention](https://github.com/korken89/wg/blob/master/rfcs/0377-mutex-trait.md#design-decisions-and-compatibility).
|
||||
///
|
||||
/// # Example
|
||||
///
|
||||
/// Since the lock function takes an `&mut self` to enable deadlock-prevention, the trait is
|
||||
/// best implemented **for a reference to a container struct**, and has a usage pattern that
|
||||
/// might feel strange at first:
|
||||
///
|
||||
/// ```
|
||||
/// static MUT: Mutex<RefCell<i32>> = Mutex::new(RefCell::new(0));
|
||||
///
|
||||
/// fn foo() {
|
||||
/// let mut r = &MUT; // Note that r is mutable
|
||||
/// r.lock(|data| *data += 1);
|
||||
/// }
|
||||
/// ```
|
||||
pub trait Mutex {
|
||||
/// Type of data encapsulated by the mutex.
|
||||
type Data;
|
||||
|
||||
/// Creates a critical section and grants temporary mutable access to the encapsulated data.
|
||||
fn lock<R>(&mut self, f: impl FnOnce(&mut Self::Data) -> R) -> R;
|
||||
}
|
||||
}
|
||||
|
||||
/// Driver interfaces.
|
||||
pub mod driver {
|
||||
/// Driver result type, e.g. for indicating successful driver init.
|
||||
pub type Result = core::result::Result<(), ()>;
|
||||
|
||||
/// Device Driver functions.
|
||||
pub trait DeviceDriver {
|
||||
/// Return a compatibility string for identifying the driver.
|
||||
fn compatible(&self) -> &str;
|
||||
|
||||
/// Called by the kernel to bring up the device.
|
||||
fn init(&self) -> Result {
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Timekeeping interfaces.
|
||||
pub mod time {
|
||||
use core::time::Duration;
|
||||
|
||||
/// Timer functions.
|
||||
pub trait Timer {
|
||||
/// The timer's resolution.
|
||||
fn resolution(&self) -> Duration;
|
||||
|
||||
/// The uptime since power-on of the device.
|
||||
///
|
||||
/// This includes time consumed by firmware and bootloaders.
|
||||
fn uptime(&self) -> Duration;
|
||||
|
||||
/// Spin for a given duration.
|
||||
fn spin_for(&self, duration: Duration);
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,97 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
// Rust embedded logo for `make doc`.
|
||||
#![doc(html_logo_url = "https://git.io/JeGIp")]
|
||||
|
||||
//! The `kernel`
|
||||
//!
|
||||
//! The `kernel` is composed by glueing together code from
|
||||
//!
|
||||
//! - [Hardware-specific Board Support Packages] (`BSPs`).
|
||||
//! - [Architecture-specific code].
|
||||
//! - HW- and architecture-agnostic `kernel` code.
|
||||
//!
|
||||
//! using the [`kernel::interface`] traits.
|
||||
//!
|
||||
//! [Hardware-specific Board Support Packages]: bsp/index.html
|
||||
//! [Architecture-specific code]: arch/index.html
|
||||
//! [`kernel::interface`]: interface/index.html
|
||||
|
||||
#![feature(format_args_nl)]
|
||||
#![feature(panic_info_message)]
|
||||
#![feature(trait_alias)]
|
||||
#![no_main]
|
||||
#![no_std]
|
||||
|
||||
// Conditionally includes the selected `architecture` code, which provides the `_start()` function,
|
||||
// the first function to run.
|
||||
mod arch;
|
||||
|
||||
// `_start()` then calls `runtime_init::init()`, which on completion, jumps to `kernel_init()`.
|
||||
mod runtime_init;
|
||||
|
||||
// Conditionally includes the selected `BSP` code.
|
||||
mod bsp;
|
||||
|
||||
mod interface;
|
||||
mod panic_wait;
|
||||
mod print;
|
||||
|
||||
/// Early init code.
|
||||
///
|
||||
/// Concerned with with initializing `BSP` and `arch` parts.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// - Only a single core must be active and running this function.
|
||||
/// - The init calls in this function must appear in the correct order.
|
||||
unsafe fn kernel_init() -> ! {
|
||||
for i in bsp::device_drivers().iter() {
|
||||
if let Err(()) = i.init() {
|
||||
// This message will only be readable if, at the time of failure, the return value of
|
||||
// `bsp::console()` is already in functioning state.
|
||||
panic!("Error loading driver: {}", i.compatible())
|
||||
}
|
||||
}
|
||||
|
||||
bsp::post_driver_init();
|
||||
|
||||
// Transition from unsafe to safe.
|
||||
kernel_main()
|
||||
}
|
||||
|
||||
/// The main function running after the early init.
|
||||
fn kernel_main() -> ! {
|
||||
use core::time::Duration;
|
||||
use interface::{console::All, time::Timer};
|
||||
|
||||
println!("Booting on: {}", bsp::board_name());
|
||||
|
||||
println!(
|
||||
"Current privilege level: {}",
|
||||
arch::state::current_privilege_level()
|
||||
);
|
||||
println!("Exception handling state:");
|
||||
arch::state::print_exception_state();
|
||||
|
||||
println!(
|
||||
"Architectural timer resolution: {} ns",
|
||||
arch::timer().resolution().as_nanos()
|
||||
);
|
||||
|
||||
println!("Drivers loaded:");
|
||||
for (i, driver) in bsp::device_drivers().iter().enumerate() {
|
||||
println!(" {}. {}", i + 1, driver.compatible());
|
||||
}
|
||||
|
||||
println!("Timer test, spinning for 1 second");
|
||||
arch::timer().spin_for(Duration::from_secs(1));
|
||||
|
||||
println!("Echoing input now");
|
||||
loop {
|
||||
let c = bsp::console().read_char();
|
||||
bsp::console().write_char(c);
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! A panic handler that infinitely waits.
|
||||
|
||||
use crate::{arch, println};
|
||||
use core::panic::PanicInfo;
|
||||
|
||||
#[panic_handler]
|
||||
fn panic(info: &PanicInfo) -> ! {
|
||||
if let Some(args) = info.message() {
|
||||
println!("Kernel panic: {}", args);
|
||||
} else {
|
||||
println!("Kernel panic!");
|
||||
}
|
||||
|
||||
arch::wait_forever()
|
||||
}
|
||||
@ -0,0 +1,91 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! Printing facilities.
|
||||
|
||||
use crate::{bsp, interface};
|
||||
use core::fmt;
|
||||
|
||||
/// Prints without a newline.
|
||||
///
|
||||
/// Carbon copy from https://doc.rust-lang.org/src/std/macros.rs.html
|
||||
#[macro_export]
|
||||
macro_rules! print {
|
||||
($($arg:tt)*) => ($crate::print::_print(format_args!($($arg)*)));
|
||||
}
|
||||
|
||||
/// Prints with a newline.
|
||||
#[macro_export]
|
||||
macro_rules! println {
|
||||
() => ($crate::print!("\n"));
|
||||
($string:expr) => ({
|
||||
#[allow(unused_imports)]
|
||||
use crate::interface::time::Timer;
|
||||
|
||||
let timestamp = $crate::arch::timer().uptime();
|
||||
let timestamp_subsec_us = timestamp.subsec_micros();
|
||||
|
||||
$crate::print::_print(format_args_nl!(
|
||||
concat!("[ {:>3}.{:03}{:03}] ", $string),
|
||||
timestamp.as_secs(),
|
||||
timestamp_subsec_us / 1_000,
|
||||
timestamp_subsec_us % 1_000
|
||||
));
|
||||
});
|
||||
($format_string:expr, $($arg:tt)*) => ({
|
||||
#[allow(unused_imports)]
|
||||
use crate::interface::time::Timer;
|
||||
|
||||
let timestamp = $crate::arch::timer().uptime();
|
||||
let timestamp_subsec_us = timestamp.subsec_micros();
|
||||
|
||||
$crate::print::_print(format_args_nl!(
|
||||
concat!("[ {:>3}.{:03}{:03}] ", $format_string),
|
||||
timestamp.as_secs(),
|
||||
timestamp_subsec_us / 1_000,
|
||||
timestamp_subsec_us % 1_000,
|
||||
$($arg)*
|
||||
));
|
||||
})
|
||||
}
|
||||
|
||||
/// Prints a warning, with newline.
|
||||
#[macro_export]
|
||||
macro_rules! warn {
|
||||
($string:expr) => ({
|
||||
#[allow(unused_imports)]
|
||||
use crate::interface::time::Timer;
|
||||
|
||||
let timestamp = $crate::arch::timer().uptime();
|
||||
let timestamp_subsec_us = timestamp.subsec_micros();
|
||||
|
||||
$crate::print::_print(format_args_nl!(
|
||||
concat!("[W {:>3}.{:03}{:03}] ", $string),
|
||||
timestamp.as_secs(),
|
||||
timestamp_subsec_us / 1_000,
|
||||
timestamp_subsec_us % 1_000
|
||||
));
|
||||
});
|
||||
($format_string:expr, $($arg:tt)*) => ({
|
||||
#[allow(unused_imports)]
|
||||
use crate::interface::time::Timer;
|
||||
|
||||
let timestamp = $crate::arch::timer().uptime();
|
||||
let timestamp_subsec_us = timestamp.subsec_micros();
|
||||
|
||||
$crate::print::_print(format_args_nl!(
|
||||
concat!("[W {:>3}.{:03}{:03}] ", $format_string),
|
||||
timestamp.as_secs(),
|
||||
timestamp_subsec_us / 1_000,
|
||||
timestamp_subsec_us % 1_000,
|
||||
$($arg)*
|
||||
));
|
||||
})
|
||||
}
|
||||
|
||||
pub fn _print(args: fmt::Arguments) {
|
||||
use interface::console::Write;
|
||||
|
||||
bsp::console().write_fmt(args).unwrap();
|
||||
}
|
||||
@ -0,0 +1,24 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
|
||||
//! Rust runtime initialization code.
|
||||
|
||||
/// Equivalent to `crt0` or `c0` code in C/C++ world. Clears the `bss` section, then jumps to kernel
|
||||
/// init code.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// - Only a single core must be active and running this function.
|
||||
pub unsafe fn init() -> ! {
|
||||
extern "C" {
|
||||
// Boundaries of the .bss section, provided by the linker script.
|
||||
static mut __bss_start: u64;
|
||||
static mut __bss_end: u64;
|
||||
}
|
||||
|
||||
// Zero out the .bss section.
|
||||
r0::zero_bss(&mut __bss_start, &mut __bss_end);
|
||||
|
||||
crate::kernel_init()
|
||||
}
|
||||
Loading…
Reference in New Issue